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PDF M54HC375 Data sheet ( Hoja de datos )

Número de pieza M54HC375
Descripción QUAD D TYPE LATCH
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M54HC375 Hoja de datos, Descripción, Manual

. HIGH SPEED
tPD = 14 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 1 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS375
M54HC375
M74HC375
QUAD D TYPE LATCH
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 37 5F 1R
M 74H C3 75 M1 R
M 74HC 37 5B 1R
M 74H C3 75 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC375 is a high speed CMOS QUAD D
TYPE LATCH fabricated in silicon gate C2MOS
technology. It has the same high speed perform-
ance of LSTTL combined with true CMOSlow power
consumption. It contains two groups of 2-bit latches
controlled by an enable input (G1 . 2 or G3 . 4).
These two latch groups can be used in the different
circuits. Each latch has Q and Q outputs (1Q to 4Q
and 1Q to 4Q). The data applied to the data input is
transferred to the Q and Q outputs when the enable
input is taken high and the outputs will follow the
data input as long as the enable input is kept high.
When the enable input is taken low, the information
data applied to the data input at that time is retained
at the outputs.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
NC =
No Internal
Connection
February 1993
1/11

1 page




M54HC375 pdf
M54/M74HC375
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(DATA - Q, Q)
2.0
4.5
6.0
56 115 145 175
14 23 29 35 ns
12 20 25 30
tPLH Propagation
tPHL Delay Time
(G - Q, Q)
2.0
4.5
6.0
52 105 130 160
13 21 26 32 ns
11 18 22 27
t(W)H
Minimum Enable
Pulse Width
(G)
2.0
4.5
6.0
12 75
3 15
3 13
95 115
19 23 ns
16 20
ts Minimum Set-up 2.0
Time
(DATA - G)
4.5
6.0
20 75
5 15
4 13
95 115
19 23 ns
16 20
th Minimum Hold 2.0
Time
(DATA - G)
4.5
6.0
000
0 0 0 ns
000
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
52
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC
5/11

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M54HC375 arduino
M54/M74HC375
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
11/11

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