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PDF M54HC173F1R Data sheet ( Hoja de datos )

Número de pieza M54HC173F1R
Descripción QUAD D-TYPE REGISTER 3-STATE
Fabricantes ST Microelectronics　
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M54HC173F1R Hoja de datos, Descripción, Manual

M54HC173
M74HC173
QUAD D-TYPE REGISTER (3-STATE)
. HIGH SPEED
fMAX = 73 MHz (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS 173
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 17 3F 1R
M 74H C1 73 M1 R
M 74HC 17 3B 1R
M 74H C1 73 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC173 is a high speed CMOS QUAD D-
TYPE REGISTER (3-STATE) fabricated in silicon
gate C2MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device is composed of a four-bit register includ-
ing D-type flip-flops and 3-state buffers. The four flip-
flops are controlled by a common clock input
(CLOCK) and a common reset input (CLEAR). Sig-
nals applied to the data inputs (D1-D4) are stored at
the respective flip-flops on the positive going transi-
tion of the clock input, only when both clock control
inputs (G1 and G2) are held low.
The reset feature is asynchronous and active high.
The stored data are provided on each output only
when both output control inputs (M and N) are held
low, otherwise the outputs go to the high-impedance
state.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
October 1992
NC =
No Internal
Connection
1/12

1 page




M54HC173F1R pdf
M54/M74HC173
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
tTLH Output Transition
tTHL Time
tPLH Propagation
tPHL Delay Time
(CLOCK - Q)
tPLH Propagation
tPHL Delay Time
(CLEAR - Q)
fMAX Maximum Clock
Frequency
tPZL Output Enable
tPZH Time
tPLZ Output Disable
tPHZ Time
tW(H)
tW(L)
tW(L)
ts
ts
th
Minimum Pulse
Width
(CLOCK)
Minimum Pulse
Width
(CLEAR)
Minimum Set-up
Time
(G1, G2)
Minimum Set-up
Time
(D)
Minimum Hold
Time
(G1, G2, D)
Test Conditions
VCC CL
(V) (pF)
2.0
4.5 50
6.0
2.0
4.5 50
6.0
2.0
4.5 150
6.0
2.0
4.5 50
6.0
2.0
4.5 150
6.0
2.0
4.5 50
6.0
2.0
4.5 50 RL = 1KΩ
6.0
2.0
4.5 150 RL = 1KΩ
6.0
2.0
4.5 50 RL = 1KΩ
6.0
2.0
4.5 50
6.0
2.0
4.5 50
6.0
2.0
4.5 50
6.0
2.0
4.5 50
6.0
2.0
4.5 50
6.0
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
25 60
7 12
6 10
50 115
14 23
12 20
65 145
18 29
15 25
50 115
14 23
12 20
65 145
18 29
15 25
8.6 20
43 67
51 84
50 115
14 23
12 20
65 145
18 29
15 25
36 105
15 21
13 18
16 75
4 15
3 13
16 75
4 15
3 13
40 100
10 20
9 17
24 75
6 15
5 13
0
0
0
Value
-40 to 85 oC
74HC
Min. Max.
75
15
13
145
29
25
180
36
31
145
29
25
180
36
31
6.8
34
40
145
29
25
180
36
31
130
26
22
95
19
16
95
19
16
125
25
21
95
19
16
0
0
0
-55 to 125 oC
54HC
Min. Max.
90
18
15
175
35
30
220
44
37
175
35
30
220
44
37
5.8
29
34
175
35
30
220
44
37
160
32
27
110
22
19
110
22
19
150
30
26
110
22
19
0
0
0
Unit
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
5/12

5 Page





M54HC173F1R arduino
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
M54/M74HC173
MIN.
9.78
8.89
4.2
7.37
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
P027A
11/12

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