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PDF M54HC109F1R Data sheet ( Hoja de datos )

Número de pieza M54HC109F1R
Descripción DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
Fabricantes ST Microelectronics 
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M54HC109
M74HC109
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 63 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS109
DESCRIPTION
The M54/74HC109 is a high speed CMOS DUAL J-
K FLIP-FLOP WITH PRESET AND CLEAR fabri-
cated in silicon gate C2MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
In accordance with the logic level on the J and K
input is device changes state on positive going tran-
sitions of the clock pulse. CLEAR and PRESET are
independent of the clock and accomplished by a low
logic level on the corresponding input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 10 9F 1R
M 74H C1 09 M1 R
M 74HC 10 9B 1R
M 74H C1 09 C1 R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
December 1992
NC =
No Internal
Connection
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1 page




M54HC109F1R pdf
M54/M74HC109
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(CK-Q, Q)
2.0
4.5
6.0
50 150 190 225
16 30 38 45 ns
13 26 32 38
tPLH Propagation
2.0
tPHL Delay Time
4.5
(CLR, PR-Q, Q) 6.0
50 150 190 225
16 30 38 45 ns
13 26 32 38
fMAX Maximum Clock 2.0
Frequency
4.5
6.2 17 5 4.2
31 59 25 21 MHz
6.0 37 67 30 25
tW(H)
tW(L)
Minimum Pulse
Width (CLOCK)
2.0
4.5
15 75
6 15
95 110
19 22 ns
6.0 6 13 16 19
tW(L) Minimum Pulse 2.0
Width (CLR, PR) 4.5
15 75
6 15
95 110
19 22 ns
6.0 6 13 16 19
ts Minimum Set-up 2.0
Time
4.5
17 75
5 15
95 110
19 22 ns
6.0 4 13 16 19
th Minimum Hold 2.0
Time
4.5
000
0 0 0 ns
6.0 0 0 0
tREM Minimum
Removal Time
(CLR, PR)
2.0
4.5
6.0
13 50 65 75
4 10 13 15 ns
39
11 13
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
41
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/2 (per Flip-flop)
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M54HC109F1R arduino
M54/M74HC109
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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