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PDF PD488588FF Data sheet ( Hoja de datos )

Número de pieza PD488588FF
Descripción 288M bits Direct Rambus DRAM for High Performance Solution
Fabricantes Elpida Memory 
Logotipo Elpida Memory Logotipo



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DATA SHEET
288M bits Direct Rambus DRAM
for High Performance Solution
µPD488588FF-C80-40 (512K words × 18 bits × 32s banks)
Description
The Direct Rambus DRAM (Direct RDRAM) is a
general purpose high-performance memory device
suitable for use in a broad range of applications
including computer memory, graphics, video, and any
other application where high bandwidth and low
latency are required.
The µPD488588FF is 288Mbits Direct Rambus DRAM
(RDRAM), organized as 16M words by 18 bits.
The use of Rambus Signaling Level (RSL) technology
permits 800MHz transfer rates while using
conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data
transfers at 1.25ns per two bytes (10ns per sixteen
bytes).
The architecture of the Direct RDRAMs allows the
highest sustained bandwidth for multiple, simultaneous
randomly addressed memory transactions.
The separate control and data buses with independent
row and column control yield over 95% bus efficiency.
The Direct RDRAM’s four banks support up to four
simultaneous transactions.
System oriented features for mobile, graphics and
large memory systems include power management,
byte masking.
The µPD488588FF is offered in a CSP horizontal
package suitable for desktop as well as low-profile
add-in card and mobile applications. Direct RDRAMs
operate from a 2.5V supply.
Features
Highest sustained bandwidth per DRAM device
— 1.6 GB/s sustained data transfer rate
— Separate control and data buses for maximized
efficiency
— Separate row and column control buses for easy
scheduling and highest performance
— 32 banks: four transactions can take place
simultaneously at full bandwidth data rates
Low latency features
— Write buffer to reduce read latency
— 3 precharge mechanisms for controller flexibility
— Interleaved transactions
Advanced power management:
— Multiple low power states allows flexibility in power
consumption versus time to active state
— Power-down self-refresh
Overdrive current mode
Organization: 2K bytes pages and 32 banks, x 18
Uses Rambus Signaling Level (RSL) for up to
800MHz operation
Package : 80-ball FBGA (µ BGA) (17.16 × 10.2)
Application
The µPD488588FF is most appropriate for the
applications, such as consumer products demanding
vivid animations, processor memory for multimedia
and 3D graphics, network processing and storage
systems requiring scalability to accommodate future
designs.
Document No. E0251N20 (Ver. 2.0)
Date Published July 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

1 page




PD488588FF pdf
µPD488588FF-C80-40
Block Diagram
DQB8..DQB0
9
RQ7..RQ5 or
ROW2..ROW0
3
1:8 Demux
CTM CTMN SCK, CMD SIO0, SIO1 CFM CFMN
22
RCLK
RQ4..RQ0 or
COL4..COL0
5
1:8 Demux
DQA8..DQA0
9
RCLK
Packet Decode
ROWR
ROWA
11 5 5 9
ROP DR BR R
AV
TCLK
Control Registers
RCLK
COLX
655
Packet Decode
COLC
555
7
REFR Power Modes DEVID
XOP DX BX COP DC BC C
MS
COLM
88
MB MA
Match
DM
Mux
Row Decode
PRER
ACT
Sense Amp DRAM Core
64x72
64x72
512x128x144
Internal DQB Data Path
72
Bank 0
72 Bank 1
99
Bank 2
Bank 13
9 Bank 14
Bank 15
Match
XOP Decode
PREX
Match
Write
Buffer
Mux Mux
Column Decode & Mask
PREC
RD, WR
64x72
72 Internal DQA Data Path
72
99
9
9
9
Bank 16
Bank 17
Bank 18
Bank 29
Bank 30
Bank 31
9
9
Data Sheet E0251N20 (Ver. 2.0)
5

5 Page





PD488588FF arduino
µPD488588FF-C80-40
Figure 2-1 Packet Formats
T0 T1 T2 T3
CTM/CFM
T8 T9 T10 T11
CTM/CFM
ROW2 DR4T DR2 BR0 BR3 RsvR R8 R5 R2
ROW1 DR4F DR1 BR1 BR4 RsvR R7 R4 R1
ROW0 DR3 DR0 BR2 RsvB AV=1 R6 R3 R0
ROW2 DR4T DR2 BR0 BR3 ROP10ROP8ROP5ROP2
ROW1 DR4F DR1 BR1 BR4 ROP9ROP7ROP4ROP1
ROW0 DR3 DR0 BR2 RsvB AV=0 ROP6ROP3ROP0
CTM/CFM
T0
ROWA Packet
T1 T2
T3
COL4 DC4 S=1
COL3 DC3
COL2 DC2 COP1
COL1 DC1 COP0
COL0 DC0 COP2
C6 C4
C5 C3
RsvB BC2 C2
BC4 BC1 C1
COP3 BC3 BC0 C0
CTM/CFM
T8
COLC Packet
T9 T10
T11
ROWR Packet
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12 T13 T14 T15
CTM/CFM
ROW2
..ROW0
COL4
..COL0
ACT a0
PRER c0
WR b1
tPACKET
MSK (b1) PREX d0
DQA8..0
DQB8..0
T12 T13 T14 T15
CTM/CFM
COL4
COL3
COL2
COL1
COL0
Note1
S=1 MA7 MA5 MA3 MA1
M=1 MA6 MA4 MA2 MA0
MB7 MB4 MB1
MB6 MB3 MB0
MB5 MB2
COL4
COL3
COL2
COL1
COL0
Note2
S=1 DX4 XOP4 RsvB BX1
M=0 DX3 XOP3 BX4 BX0
DX2 XOP2 BX3
DX1 XOP1 BX2
DX0 XOP0
COLM Packet
COLX Packet
Notes 1. The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated
by the Start bit (S=1) position.
2. The COLX is aligned with the present COLC, indicates by the Start bit (S=1) position.
Data Sheet E0251N20 (Ver. 2.0)
11

11 Page







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