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PDF EL1881 Data sheet ( Hoja de datos )

Número de pieza EL1881
Descripción Sync Separator/ Low Power
Fabricantes Intersil 
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No Preview Available ! EL1881 Hoja de datos, Descripción, Manual

®
Data Sheet
October 20, 2004
EL1881
FN7018.1
Sync Separator, Low Power
The EL1881 video sync separator is manufactured using
Elantec’s high performance analog CMOS process. This
device extracts sync timing information from both standard
and non-standard video input. It provides composite sync,
vertical sync, burst/back porch timing, and odd/even field
detection. Fixed 70mV sync tip slicing provides sync edge
detection when the video input level is between 0.5VP-P and
-2VP-P (sync tip amplitude 143mV to 572mV). A single
external resistor sets all internal timing to adjust for various
video standards. The composite sync output follows video in
sync pulses and a vertical sync pulse is output on the rising
edge of the first vertical serration following the vertical pre-
equalizing string. For non-standard vertical inputs, a default
vertical pulse is output when the vertical signal stays low for
longer than the vertical sync default delay time. The
odd/even output indicates field polarity detected during the
vertical blanking interval. The EL1881 is plug-in compatible
with the industry-standard LM1881 and can be substituted
for that part in 5V applications with lower required supply
current.
The EL1881 is available in the 8-pin PDIP and SO packages
and is specified for operation over the full -40°C to +85°C
temperature range.
Ordering Information
PART NUMBER
PKG.
PACKAGE TAPE & REEL DWG. #
EL1881CN
8-Pin PDIP
- MDP0031
EL1881CS
8-Pin SO
- MDP0027
EL1881CS-T7
8-Pin SO
7” MDP0027
EL1881CS-T13
8-Pin SO
13” MDP0027
EL1881CSZ
(See Note)
8-Pin SO
(Pb-free)
- MDP0027
EL1881CSZ-T7
(See Note)
8-Pin SO
(Pb-free)
7” MDP0027
EL1881CSZ-T13
(See Note)
8-Pin SO
(Pb-free)
13” MDP0027
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
Features
• NTSC, PAL, SECAM, non-standard video sync separation
• Fixed 70mV slicing of video input levels from 0.5VP-P to
2VP-P
• Low supply current - 1.5mA typ.
• Single +5V supply
• Composite, vertical sync output
• Odd/even field output
• Burst/back porch output
• Available in 8-pin PDIP and SO packages
Pb-free available
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
• Line drivers
• Portable computers
• High-speed communications
• RGB applications
• Broadcast equipment
• Active filtering
Demo Board
A dedicated demo board is available.
Pinout
EL1881
(8-PIN PDIP, SO)
TOP VIEW
COMPOSITE SYNC OUT 1
COMPOSITE VIDEO IN 2
VERTICAL SYNC OUT 3
GND 4
8 VDD 5V
7 ODD/EVEN OUTPUT
6 RSET
5 BUST/BACK
PORCH OUTPUT
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.

1 page




EL1881 pdf
EL1881C
Typical Performance Curves (Continued)
Burst/Back Porch Width vs RSET
VDD=5V, TA=25°C
6
5
4
3
2
1
200 400 600 800
RSET (k)
1000
Burst/Back Porch Delay vs RSET
VDD=5V, TA=25°C
350
300
250
200
150
100
50
0
200 400 600 800
RSET (k)
1000
Vertical Sync Width vs RSET
VDD=5V, TA=25°C
350
300
250
200
150
100
50
0
200 400 600
RSET (k)
800
1000
Vertical Default Delay vs RSET
VDD=5V, TA=25°C
120
100
80
60
40
20
0
200 400 600
RSET (k)
800
1000
Composite Sync Prop Delay vs Temperature
41
39
37
35
33
31
-50
-25
0 25 50
Temperature (°C)
75 100
Burst/Back Porch Width vs Temperature
3.9
3.8
3.7
3.6
5.5V
3.5
3.4 5V 4.5V
3.3
3.2
3.1
-50
-25
0 25 50
Temperature (°C)
75
100
5 FN7018.1

5 Page





EL1881 arduino
Simplified Block Diagram
EL1881C
SYNC TIP
REF
1.5V
CLAMP
RF
620CF
510pF
COMPOSITE
C1 VIDEO IN
2
0.1µF
GND 4
C3
0.1µF
RSET*
RSET 6
SLICE
1.57V
REF
GEN
SYNC
TIP
70mV
SLICE
VDD
COMP.
-
+
8 VDD
5V
C2
0.1µF
1 COMPOSITE
SYNC
BURST
5 BURST/BACK
PORCH OUT
VERT SYNC
3 VERTICAL
SYNC OUT
NOTE: * RSET MUST BE AT 1% RESISTOR
FIGURE 6.
ODD/EVEN
7 ODD/EVEN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN7018.1

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