PDF EDI88128P Data sheet ( Hoja de datos )

Número de pieza	EDI88128P
Descripción	128K X 8 STATIC RAM CMOS MONOLITHIC
Fabricantes	ETC
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No Preview Available ! EDI88128C 128KX8 MONOLITHIC SRAM, SMD 5962-89598 FEATURES n Access Times of 70, 85, 100ns n Available with Single Chip Selects (EDI88128) or Dual Chip Selects (EDI88130) n 2V Data Retention (LP Versions) n CS and OE Functions for Bus Control n TTL Compatible Inputs and Outputs n Fully Static, No Clocks n Organized as 128Kx8 n Industrial, Military and Commercial Temperature Ranges n Thru-hole and Surface Mount Packages JEDEC Pinout • 32 pin Ceramic DIP, 0.6 mils wide (Package 9) • 32 lead Ceramic SOJ (Package 140) n Single +5V (±10%) Supply Operation The EDI88128C is a high speed, high performance, Mono- lithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (CS2) can be used to provide system memory security during power down in non-battery backed up systems and simplifiy decoding schemes in memory banking where large multiple pages of memory are required. The EDI88128C and the EDI88130C have eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. Low power versions, EDI88128LP and EDI88130LP, offer a 2V data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535. FIG. 1 P CIN ONFIGURATION 32 DIP 32 SOJ T VOP IEW NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 AØ 12 I/OØ 13 I/O1 14 I/O2 15 VSS 16 32 VCC 31 A15 30 NC/CS2* 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS1 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 P DIN ESCRIPTION I/O0-7 Data Inputs/Outputs A0-16 Address Inputs WE Write Enable CS1, CS2 Chip Selects OE Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected B DLOCK IAGRAM * Pin 30 is NC for 88128 or CS2 for 88130. March 2002 Rev. 16 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 1 page EDI88128C F . 2 T W - R CIG IMING AVEFORM EAD YCLE ADDRESS DATA I/O tAVAV ADDRESS 1 tAVQV ADDRESS 2 tAVQX DATA 1 READ CYCLE 1 (WE HIGH; OE, CS LOW) DATA 2 ADDRESS CS1 CS2 OE DATA I/O tAVAV tAVQV tELQV tELQX tSHQV tSHQX tGLQV tGLQX READ CYCLE 2 (WE HIGH) tEHQZ tSLQZ tGHQZ F . 3 W C 1IG RITE YCLE ADDRESS WE CS1 CS2 DATA IN DATA OUT tAVWL tAVAV tAVWH tWLWH tWHAX tELWH tSHWH tWLQZ tDVWH tWHQX tWHDX DATA VALID HIGH Z WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED F . 4 W C 2IG RITE YCLE ADDRESS WE CS1 CS2 DATA IN tAVEL tAVAV tWLEH tELEH tEHAX tDVEH tEHDX DATA VALID WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED W C 3RITE YCLE WS32K32-XHX ADDRESS tAVSH WE tAVAV tWLSL tSHSL CS1 tSLAX CS2 DATA IN tDVSL tSLDX DATA VALID WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 5 Page

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Número de pieza	Descripción	Fabricantes
EDI88128C	128K X 8 STATIC RAM CMOS MONOLITHIC	ETC
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EDI88128CS	128Kx8 Monolithic SRAM	White Electronic Designs
EDI88128LP	128K X 8 STATIC RAM CMOS MONOLITHIC	ETC

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