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PDF EDD5104ABTA Data sheet ( Hoja de datos )
| Número de pieza | EDD5104ABTA | |
| Descripción | 512M bits DDR SDRAM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
512M bits DDR SDRAM
EDD5104ABTA (128M words × 4 bits)
EDD5108ABTA (64M words × 8 bits)
Description
The EDD5104AB is a 512M bits Double Data Rate
(DDR) SDRAM organized as 33,554,432 words × 4 bits
× 4 banks. The EDD5108AB is a 512M bits DDR
SDRAM organized as 16,777,216 words × 8 bits × 4
banks. Read and write operations are performed at the
cross points of the CK and the /CK. This high-speed
data transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
They are packaged in standard 66-pin plastic TSOP
(II)10.16mm(400).
Features
• 2.5 V power supply: VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
• Data Rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• 2.5 V (SSTL_2 compatible) I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
Pin Configurations
/xxx indicates active low signal.
66-pin TSOP(II)10.16mm(400)
VDD VDD
NC DQ0
VDDQ VDDQ
NC NC
DQ0 DQ1
VSSQ VSSQ
NC NC
NC DQ2
VDDQ VDDQ
NC NC
DQ1 DQ3
VSSQ VSSQ
NC NC
NC NC
VDDQ VDDQ
NC NC
NC NC
VDD VDD
NC NC
NC NC
/WE /WE
/CAS /CAS
/RAS /RAS
/CS /CS
NC NC
BA0 BA0
BA1 BA1
A10(AP) A10(AP)
A0 A0
A1 A1
A2 A2
A3 A3
VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 VSS VSS
65 DQ7 NC
64 VSSQ VSSQ
63 NC NC
62 DQ6 DQ3
61 VDDQ VDDQ
60 NC NC
59 DQ5 NC
58 VSSQ VSSQ
57 NC NC
56 DQ4 DQ2
55 VDDQ VDDQ
54 NC NC
53 NC NC
52 VSSQ VSSQ
51 DQS DQS
50 NC NC
49 VREF VREF
48 VSS VSS
47 DM DM
46 /CK /CK
45 CK CK
44 CKE CKE
43 NC NC
42 A12 A12
41 A11 A11
40 A9 A9
39 A8 A8
38 A7 A7
37 A6 A6
36 A5 A5
35 A4 A4
34 VSS VSS
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
X8
X4
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0237E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
1 page  
EDD5104ABTA, EDD5108ABTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
max.
Parameter
Symbol Grade
×4
×8
Unit Test condition
Notes
Operating current (ACT-PRE) IDD0
-6B
-7A, -7B
150
135
150
135
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 9
Operating current
(ACT-READ-PRE)
IDD1
-6B
-7A, -7B
170
155
180
160
CKE ≥ VIH, BL = 4,
mA CL = 2.5,
tRC = tRC (min.)
1, 2, 5
Idle power down standby
current
IDD2P
3
3
mA CKE ≤ VIL
4
Floating idle standby current IDD2F
-6B
-7A, -7B
40
35
40
35
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
4, 5
Quiet idle standby current IDD2Q
25
25
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
4, 10
Active power down standby
current
IDD3P
20
20
mA CKE ≤ VIL
3
Active standby current
IDD3N
-6B
-7A, -7B
70
60
70
60
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
3, 5, 6
Operating current
(Burst read operation)
IDD4R
-6B
-7A, -7B
200
170
210
180
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5,
6
Operating current
(Burst write operation)
IDD4W
-6B
-7A, -7B
200
170
210
180
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5,
6
Auto Refresh current
IDD5
-6B
-7A, -7B
290
270
290
270
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Self refresh current
IDD6
4
4
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Operating current
(4 banks interleaving)
IDD7A
-6B
-7A, -7B
420
360
430
370
mA BL = 4
5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Input leakage current
Output leakage current
Output high current
Output low current
Symbol
IL
IOZ
IOH
IOL
min.
–2
–5
–15.2
15.2
max.
2
5
—
—
Unit Test condition
µA VDD ≥ VIN ≥ VSS
µA VDDQ ≥ VOUT ≥ VSS
mA VOUT = 1.95V
mA VOUT = 0.35V
Notes
Preliminary Data Sheet E0237E30 (Ver. 3.0)
5
5 Page 
EDD5104ABTA, EDD5108ABTA
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 toA12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A9, A11 and A12 at the cross point of the CK rising edge and the /CK falling edge in a read or a write
command cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDD5104AB
AX0 to AX12
AY0 to AY9, AY11, AY12
EDD5108AB
AX0 to AX12
AY0 to AY9, AY11,
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write
command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL
Preliminary Data Sheet E0237E30 (Ver. 3.0)
11
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