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PDF ICL7135 Data sheet ( Hoja de datos )
| Número de pieza | ICL7135 | |
| Descripción | 41/ Digit/ BCD Output/ A/D Converter | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Data Sheet
41/2 Digit, BCD Output, A/D Converter
The Intersil ICL7135 precision A/D converter, with its
multiplexed BCD output and digit drivers, combines dual-
slope conversion reliability with ±1 in 20,000 count accuracy
and is ideally suited for the visual display DVM/DPM market.
The 2.0000V full scale capability, auto-zero, and auto-
polarity are combined with true ratiometric operation, almost
ideal differential linearity and true differential input. All
necessary active devices are contained on a single CMOS
lC, with the exception of display drivers, reference, and a
clock.
The ICL7135 brings together an unprecedented combination
of high accuracy, versatility, and true economy. It features
auto-zero to less than 10μV, zero drift of less than 1μV/oC,
input bias current of 10pA (Max), and rollover error of less
than one count. The versatility of multiplexed BCD outputs is
increased by the addition of several pins which allow it to
operate in more sophisticated systems. These include
STROBE, OVERRANGE, UNDERRANGE, RUN/HOLD and
BUSY lines, making it possible to interface the circuit to a
microprocessor or UART.
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
ICL7135CPI ICL7135CPI 0 to +70 28 Ld PDIP
E28.6
ICL7135CPIZ ICL7135CPIZ 0 to +70 28 Ld PDIP
E28.6
(Note 1)
(Pb-free) (Note 2)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
2. Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
August 28, 2007
ICL7135
FN3093.4
Features
• Accuracy Guaranteed to ±1 Count Over Entire ±20000
Counts (2.0000V Full Scale)
• Guaranteed Zero Reading for 0V Input
• 1pA Typical Input Leakage Current
• True Differential Input
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage Required
• Overrange and Underrange Signals Available for Auto-
Range Capability
• All Outputs TTL Compatible
• Blinking Outputs Gives Visual Indication of Overrange
• Six Auxiliary Inputs/Outputs are Available for Interfacing to
UARTs, Microprocessors, or Other Circuitry
• Multiplexed BCD Outputs
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ICL7135
(PDIP)
TOP VIEW
V- 1
REFERENCE 2
NALOG COMMON 3
INT OUT 4
AZ IN 5
BUFF OUT 6
REF CAP - 7
REF CAP + 8
IN LO 9
IN HI 10
V+ 11
(MSD) D5 12
(LSB) B1 13
B2 14
28 UNDERRANGE
27 OVERRANGE
26 STROBE
25 R/H
24 DIGITAL GND
23 POL
22 CLOCK IN
21 BUSY
20 (LSD) D1
19 D2
18 D3
17 D4
16 (MSB) B8
15 B4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ICL7135
Detailed Description
Analog Section
Figure 3 shows the Block Diagram of the Analog Section for
the ICL7135. Each measurement cycle is divided into four
phases. They are (1) auto-zero (AZ), (2) signal-integrate
(INT), (3) de-integrate (DE) and (4) zero-integrator (Zl).
Auto-Zero Phase
During auto-zero, three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor CAZ to compensate
for offset voltages in the buffer amplifier, integrator, and
comparator. Since the comparator is included in the loop, the
AZ accuracy is limited only by the noise of the system. In any
case, the offset referred to the input is less than 10μV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO for a
fixed time. This differential voltage can be within a wide
common mode range; within one volt of either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog COMMON
to establish the correct common-mode voltage. At the end of
this phase, the polarity of the integrated signal is latched into
the polarity F/F.
De-Integrate Phase
The third phase is de-integrate or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the inte-
grator output to return to zero. The time required for the out-
put to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
OUTPUT COUNT
=
10,000
⎛
⎜
⎝
V---V--R---I-EN----F- ⎠⎟⎞
.
Zero Integrator Phase
The final phase is zero integrator. First, input low is shorted
to analog COMMON. Second, a feedback loop is closed
around the system to input high to cause the integrator
output to return to zero. Under normal condition, this phase
lasts from 100 to 200 clock pulses, but after an overrange
conversion, it is extended to 6200 clock pulses.
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier; or specifically from
0.5V below the positive supply to 1V above the negative
supply. In this range the system has a CMRR of 86dB typical.
However, since the integrator also swings with the common
mode voltage, care must be exercised to assure the integrator
output does not saturate. A worst case condition would be a
large positive common-mode voltage with a near full scale
negative differential input voltage. The negative input signal
drives the integrator positive when most of its swing has been
used up by the positive common mode voltage. For these
critical applications the integrator swing can be reduced to
less than the recommended 4V full scale swing with some
loss of accuracy. The integrator output can swing within 0.3V
of either supply without loss of linearity.
Analog COMMON
Analog COMMON is used as the input low return during auto-
zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system and
is taken care of by the excellent CMRR of the converter.
However, in most applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The reference voltage is referenced to analog
COMMON.
Reference
The reference input must be generated as a positive voltage
with respect to COMMON, as shown in Figure 4.
V+
REF HI
ICL7135
COMMON
6.8V
ZENER
IZ
V-
FIGURE 4A.
V+
V+
REF HI 20kΩ
ICL7135
6.8kΩ
ICL8069
1.2V
REFERENCE
COMMON
FIGURE 4B.
FIGURE 4. USING AN EXTERNAL REFERENCE
5 FN3093.4
5 Page 
ICL7135
REF
VOLTAGE
-5V
1 V-
ICL7135 UR 28
2 REF
OR 27
ANALOG
GND
100kΩ
27Ω
3
ANALOG
COMMON
4 INT OUT
0.47μF 5 AZIN
1μF 6 BUF OUT
100kΩ
7 RC1
1μF
8 RC2
STROBE 26
R/H 25
DIG. GND 24
POL 23
CLOCK 22
BUSY 21
+5V
100kΩ
INPUT 0.1μF
9 INPUT LO
10 INPUT HI
+5V 11 V+
D1 20
D2 19
D3 18
12 D5
D4 17
13 B1
B8 16
14 B2
B4 15
41/2 DIGIT LCD DISPLAY
28 SEGMENTS D1-D4
1 16 15 1412 5 3 4
CD4054A
7 8 13 1110 9 2 6
120kC = 3 READINGS/SEC
CLOCK IN
300pF
BACKPLANE
5BP ICM7211A
31 D1
32 D2
33 D3
34 D4
30 B3
29 B2
28 B1
27 B0
35 V-
2,3,4
6-26
37-40
OSC 36
OPTIONAL
CAPACITOR
22-100pF +5V
V+ 1
FIGURE 10. DRIVING LCD DISPLAYS
0V
+5V
+5V
0.22μF
16kΩ
56kΩ
8
2
+
LM311
7
3- 4 1
16kΩ
1kΩ
30kΩ
390pF
FIGURE 11. LM311 CLOCK SOURCE
+
10μF -
+5V
18
27
ICL7660
36
4 5 - VOUT = -5V
10μF +
FIGURE 12. GENERATING A NEGATIVE SUPPLY FROM +5V
11 FN3093.4
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICL7135.PDF ] | |
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