PDF ICL7129CM44 Data sheet ( Hoja de datos )

Número de pieza	ICL7129CM44
Descripción	41/2 Digit LCD/ Single-Chip A/D Converter
Fabricantes	Intersil
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No Preview Available ! ICL7129 August 1997 41/2 Digit LCD, Single-Chip A/D Converter Features • ±19,999 Count A/D Converter Accurate to ±4 Count • 10µV Resolution on 200mV Scale • 110dB CMRR • Direct LCD Display Drive • True Differential Input and Reference • Low Power Consumption • Decimal Point Drive Outputs • Overrange and Underrange Outputs • Low Battery Detection and Indication • 10:1 Range Change Input Ordering Information TEMP. PART NUMBER RANGE (oC) PACKAGE ICL7129CPL 0 to 70 40 Ld PDIP ICL7129RCPL 0 to 70 40 Ld PDIP ICL7129CM44 0 to 70 44 Ld MQFP NOTE: “R” indicates device with reversed leads. PKG. NO. E40.6 E40.6 Q44.10x10 Description The Intersil ICL7129 is a very high performance 41/2-digit, analog-to-digital converter that directly drives a multiplexed liquid crystal display. This single chip CMOS integrated cir- cuit requires only a few passive components and a reference to operate. It is ideal for high resolution hand-held digital multimeter applications. The performance of the ICL7129 has not been equaled before in a single chip A/D converter. The successive integra- tion technique used in the ICL7129 results in accuracy better than 0.005% of full scale and resolution down to 10µV/count. The ICL7129, drawing only 1mA from a 9V battery, is well suited for battery powered instruments. Provision has been made for the detection and indication of a “LOW/BATTERY” condition. Autoranging instruments can be made with the ICL7129 which provides overrange and underrange outputs and 10:1 range changing input. The ICL7129 instantly checks for continuity, giving both a visual indication and a logic level output which can enable an external audible transducer. These features and the high performance of the ICL7129 make it an extremely versatile and accurate instrument-on-a-chip. Pinouts ICL7129 (PDIP) TOP VIEW OSC1 1 OSC3 2 ANNUNCIATOR DRIVE 3 B1, C1, CONT 4 A1, G1, D1 5 F1, E1, DP1 6 B2, C2, LO BAT 7 A2, G2, D2 8 F2, E2, DP2 9 B3, C3, MINUS 10 A3, G3, D3 11 F3, E3, DP3 12 B4, C4, BC5 13 A4, D4, G4 14 F4, E4, DP4 15 BP3 16 BP2 17 BP1 18 VDISP 19 DP4/OR 20 40 OSC2 39 DP1 38 DP2 37 RANGE 36 DGND 35 REF LO 34 REF HI 33 IN HI 32 IN LO 31 BUFF 30 CREF- 29 CREF+ 28 COMMON 27 CONTINUITY 26 INT OUT 25 INT IN 24 V+ 23 V- 22 LATCH/HOLD 21 DP3/UR ICL7129 (MQFP) TOP VIEW DGND RANGE DP2 DP1 OSC 2 OSC 1 OSC 3 NC NC ANNUNCE DRIVE B1, C1, CONT 144 43 42 41 40 39 38 37 36 35 34 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 V+ V- NC NC LATCH/ HOLD DP3/UR DP4/OR VDISP BP1 BP2 BP3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 3-31 File Number 3085.1 1 page ICL7129 Detailed Description The ICL7129 is a uniquely designed single chip A/D converter. It features a new “successive integration” technique to achieve 10µV resolution on a 200mV full-scale range. To achieve this resolution a 10:1 improvement in noise performance over previous monolithic CMOS A/D converters was accomplished. Previous integrating converters used an external capacitor to store an offset correction voltage. This technique worked well but greatly increased the equivalent noise bandwidth of the converter. The ICL7129 removes this source of error (noise) by not using an auto-zero capacitor. Offsets are cancelled using digital techniques instead. Savings in external parts cost are realized as well as improved noise performance and elimination of a source of electromagnetic and electrostatic pick-up. In the overall Functional Block Diagram of the ICL7129 the heart of this A/D converter is the sequence counter/decoder which drives the control logic and keeps track of the many separate phases required for each conversion cycle. The sequence counter is constantly running and is a separate counter from the up/down results counter which is activated only when the integrator is de-integrating. At the end of a con- version the data remaining in the results counter is latched, decoded and multiplexed to the liquid crystal display. The analog section block diagram shown in Figure 1 includes all of the analog switches used to conﬁgure the volt- age sources and ampliﬁers in the different phases of the cycle. The input and reference switching schemes are very similar to those in other less accurate integrating A/D con- verters. There are 5 basic conﬁgurations used in the full con- version cycle. Figure 2 illustrates a typical waveform on the integrator output. INT, INT1, and INT2 all refer to the signal integrate phase where the input voltage is applied to the integrator ampliﬁer via the buffer ampliﬁer. In this phase, the integrator ramps over a ﬁxed period of time in a direction opposite to the polarity of the input voltage. DE1, DE2, and DE3 are the de-integrate phases where the reference capacitor is switched in series with the buffer ampli- ﬁer and the integrator ramps back down to the level it started from before integrating. However, since the de-integrate phase can terminate only at a clock pulse transition, there is always a small overshoot of the integrator past the starting point. The ICL7129 ampliﬁes this overshoot by 10 and DE2 begins. Simi- larly end DE2’s overshoot is ampliﬁed by 10 of DE3 the results counter holds a naunmd bDeEr3wbitehg5in1s/.2Adtigthites of resolution. This was obtained by feeding counts into the results counter at digit level during the 31/2 digit DE2 and the level 51/2 during DE1, into the digit level for DE3. 41/2 The effects of offset in the buffer, integrator, and comparator can now be cancelled by repeating this entire sequence with the inputs shorted and subtracting the results from the original reading. For this phase INT2 switch is closed to give the same common-mode voltage as the measurement cycle. This assures excellent CMRR. At the end of the cycle the data in the up/down results counter is accurate to 0.02% of full scale and is sent to the display driver for decoding and multiplexing. CREF RINT CINT REF HI REF LO BUFFER INT, IN INT OUT DE DE IN HI INT1 DE- COMMON IN LO DE+ INT1, INT2 - + DE+ BUFFER Z1, X10 DE- INT REST, INT2 10 - + 100 INTEGRATOR X10 COMPARATOR 1 + - +- TO DIGITAL SECTION COMPARATOR 2 FIGURE 1. ANALOG BLOCK DIAGRAM ZERO-INTEGRATE AND LATCH INT1 INTEGRATE DE1 DE-INTEGRATE REST X10 DE2 REST X10 DE3 ZERO-INTEGRATE NOTE: Shaded area greatly expanded in time and amplitude. 1000 CLOCKS 10,000 CLOCKS 2000 CLOCKS INTEGRATOR RESIDUE VOLTAGE 1000 CLOCKS FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND RESIDUE VOLTAGE 3-35 5 Page ICL7129 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Ofﬁce Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 3-41 11 Page

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