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PDF FRX130D1 Data sheet ( Hoja de datos )

Número de pieza FRX130D1
Descripción Radiation Hardened N-Channel Power MOSFETs
Fabricantes Intersil 
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No Preview Available ! FRX130D1 Hoja de datos, Descripción, Manual

April 1998
FRX130D, FRX130R,
FRX130H
Radiation Hardened
N-Channel Power MOSFETs
Features
Description
• 6A, 100V, rDS(ON) = 0.180
• Second Generation Rad Hard MOSFET Results From
New Design Concepts
• Gamma
- Meets Pre-RAD Specifications to 100K RAD (Si)
- Defined End-Point Specs at 300K RAD (Si) and
1000K RAD (Si)
- Performance Permits Limited Use to 3000K RAD (Si)
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BVDSS
- Typically Survives 2E12 if Current Limited to IDM
• Photo Current
- 1.50nA Per-RAD (Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm2
- Usable to 3E14 Neutrons/cm2
Ordering Information
PART NUMBER
PACKAGE
BRAND
The Intersil has designed a series of SECOND GENERA-
TION hardened power MOSFETs of both N-Channel and
P-Channel enhancement types with ratings from 100V to
500V, 1A to 60A, and on resistance as low as 25m. Total
dose hardness is offered at 100K RAD (Si) and 1000K RAD
(Si) with neutron hardness ranging from 1E13n/cm2 for
500V product to 1E14n/cm2 for 100V product. Dose rate
hardness (GAMMA DOT) exists for rates to 1E9 without
current limiting and 2E12 with current limiting.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to exhibit mini-
mal characteristic changes to total dose (GAMMA) and
neutron (no) exposures. Design and processing efforts are
also directed to enhance survival to heavy ion (SEU) and/or
dose rate (GAMMA DOT) exposure.
This part may be supplied as a die or in various packages
other than shown above. Reliability screening is available
as either non TX (commercial), TX equivalent of MIL-S-
19500, TXV equivalent of MIL-S-19500, or space equiva-
lent of MIL-S-19500. Contact the Intersil High-Reliability
Marketing group for any desired deviations from the data
sheet.
FRX130D1
FRX130D3
FRX130R1
18 Ld CLCC
18 Ld CLCC
18 Ld CLCC
FRX130D1
FRX130D3
FRX130R1
Symbol
D
FRX130R3
FRX130R4
18 Ld CLCC
18 Ld CLCC
FRX130R3
FRX130R4
G
FRX130H4
18 Ld CLCC
FRX130H4
S
Package
18 LEAD CLCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3144.3

1 page




FRX130D1 pdf
FRX130D, FRX130R, FRX130H
18 Pin CLCC
18 PIN CERAMIC LEADLESS CHIP CARRIER
E
R1
D
A
D2
D1
L1
R
E1
E2
SEATING
PLANE
e
1
2
b
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.092
0.112
2.34
2.84
-
b
0.020
0.030
0.51
0.76
-
D
0.275
0.295
6.99
7.49
-
D1
0.175
0.215
4.45
5.46
D2
0.070
0.080
1.78
2.03
E
0.340
0.360
8.64
9.14
-
-
-
E1
0.240
0.280
6.10
7.11
E2
0.095
0.105
2.42
2.66
e 0.050 BSC
1.27 BSC
-
-
-
L
0.085
0.115
2.16
2.92
-
L1
0.035
0.055
0.89
1.39
R
0.007
0.017
0.18
0.43
-
4
R1
NOTES:
0.003
0.013
0.08
0.33
4
1. No current JEDEC outline for this package.
2. All exposed metallized areas shall be plated with a minimum of 50
microinches of gold over nickel unless otherwise stated.
3. Metallized castellations shall be connected to the seating plane
and extend upward toward top of package.
4. Corner shape (notch, radius, square, etc.) may vary at the manu-
facturer's option.
5. Unless otherwise specified, a minimum clearance of 0.010 inches
(0.25mm) shall be maintained between all metallized areas.
6. Controlling dimension: Inch.
7. Revision 1 dated 6-93.
L
ELEMENT
GATE
DRAIN
SOURCE
PAD
A
B
C
PINS CONNECTED
5
1, 2, 3, 4, 16, 17, 18
6, 7, 8, 9, 10, 11, 12, 13, 14, 15
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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