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PDF TDA7339 Data sheet ( Hoja de datos )
| Número de pieza | TDA7339 | |
| Descripción | 3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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® TDA7339
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEW
THREE STEREO INPUT
ONE RECORD OUTPUT
ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DIP28
DESCRIPTION
The TDA7339 is a volume and tone (bass , mid-
dle and treble) processor for quality audio appli-
cation in car radio and Hi-Fi system.
Control is accomplished by serial I2C bus micro-
processor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
BLOCK DIAGRAM
ORDERING NUMBER: TDA7339
Thanks to the used BIPOLAR/MOS Technology,
Low Distortion, Low Noise and Low DC stepping
are obtained.
IN1(L)
IN2(L)
IN3(L)
IN1(R)
IN2(R)
IN3(R)
3x
2.2µF
C1
C2
C3
2
4
5
R1
2.7K
C7
5.6nF
REC OUT(L) TREBLE(L)
83
C9
18nF
M IN(L)
6
C10
22nF
M OUT(L)
7
1st VOL
TREBLE
MIDDLE
MUTE
R3
2.7K
C13
100nF
C14
100nF
B IN(L)
B OUT(L)
9 10
BASS
SOFTMUTE
C4
C5
C6
3x
2.2µF
MULTIPLEXER
27
25
24
MUTE
1st VOL
TREBLE
SERIAL BUS DECODE & LATCHES
MIDDLE
BASS
SOFTMUTE
1
VS SUPPLY
16 28 21
26 23
22
ANAL.GND CREF REC OUT(R) TREBLE(R) M IN(R) M OUT(R)
CREF
10µF
C8
5.6nF
C11
18nF
C12
22nF
20
B IN(R)
C15
100nF
19
B OUT(R)
C16
100nF
R2
2.7K
R4
5.6K
2nd VOL
12
OUT L
14
SCL
13
SDA
18
ADDR
15
DIG.GND
11 CMUTE
BUS
2nd VOL
17
CSM 22nF
OUT R
D94AU067C
July 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/12
1 page  
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Data Validity on the I2CBUS
TDA7339
Acknowledge
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simplier transmis-
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Timing Diagram of I2CBUS
Acknowledge on the I2CBUS
5/12
5 Page 
DIM.
MIN.
mm
TYP. MAX. MIN.
inch
TYP. MAX.
a1 0.63
0.025
b 0.45
0.018
b1 0.23
0.31 0.009
0.012
b2 1.27
0.050
D
37.34
1.470
E 15.2
16.68 0.598
0.657
e 2.54
0.100
e3 33.02
1.300
F 14.1 0.555
I 4.445
0.175
L 3.3
0.130
TDA7339
OUTLINE AND
MECHANICAL DATA
DIP28
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet TDA7339.PDF ] | |
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