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PDF TDA6503 Data sheet ( Hoja de datos )

Número de pieza TDA6503
Descripción 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
TDA6502; TDA6502A; TDA6503;
TDA6503A
5 V mixers/oscillators and
synthesizers for cable TV and VCR
2-band tuners
Preliminary specification
Supersedes data of 2000 Jan 24
File under Integrated Circuits, IC02
2000 Mar 16

1 page




TDA6503 pdf
Philips Semiconductors
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
4 QUICK REFERENCE DATA
Measured over full voltage and temperature ranges.
SYMBOL
VCC
ICC
PARAMETER
supply voltage
supply current
fXTAL
Io(PMOS)
Ptot
Tstg
Tamb
fRF
crystal oscillator frequency
PMOS port output current
total power dissipation
IC storage temperature
ambient temperature
RF frequency
GV voltage gain
NF noise figure
Vo output voltage (causing 1% cross
modulation in channel)
CONDITIONS
operating
all PMOS ports are off;
VCC = 5V
note 1
note 2
VHF band
UHF band
VHF band
UHF band
VHF band
UHF band
VHF band
UHF band
Notes
1. One buffer ‘on’, Io = 25 mA; two buffers ‘on’, maximum sum of Io = 30 mA.
2. The power dissipation is calculated as follows:
Ptot = VCC × (ICC Io) + VP(sat) × Io + (---0---.--5-2---2-×----k-3---3----V----)--2-
where:
VP(sat) = output saturation voltage on the buffer output
Io = source current for one buffer output.
MIN.
4.5
TYP.
5
71
MAX. UNIT
5.5 V
mA
4.0 MHz
− − 30 mA
− − 520 mW
40
+150 °C
20
+85 °C
40
800 MHz
200
900 MHz
20 dB
32 dB
7.5 dB
7 dB
110 dBµV
110 dBµV
5 ORDERING INFORMATION
TYPE
NUMBER
TDA6502;
TDA6502A;
TDA6503;
TDA6503A
NAME
SSOP28
PACKAGE
DESCRIPTION
plastic shrink small outline package; 28 leads; body width 5.3 mm
VERSION
SOT341-1
2000 Mar 16
5

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TDA6503 arduino
Philips Semiconductors
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
Table 8 Reference divider ratio select bits
RSA
X
0
1
RSB
0
1
1
REFERENCE DIVIDER RATIO
80
1 28
64
FREQUENCY STEP (kHz)
50
31.25
62.5
8.2.3 READ MODE
The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9).
After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is
transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data
byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge).
End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1)
A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC
information to the microcontroller of the IF section of the television.
Table 9 Read data format
NAME
BYTE
Address byte
Status byte
ADB
SB
Note
1. MSB is transmitted first.
MSB(1)
1
POR
1
FL
0
R
BIT
00
11
MA1
A2
MA0
A1
LSB
R/W = 1
A0
Table 10 Description of the bits used in Table 9
BIT
MA1 and MA0
R/W
POR
FL
R
A2, A1 and A0
DESCRIPTION
programmable address bits (see Table 6)
logic 1 for read mode
Power-on reset flag:
logic 0: at power-off
logic 1: at power-on
in-lock flag:
logic 0: loop is not locked
logic 1: loop is locked
ready flag:
logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked
logic 1: in other conditions
digital outputs of the 5-level ADC (see Table 11)
2000 Mar 16
11

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