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PDF TDA5360 Data sheet ( Hoja de datos )

Número de pieza TDA5360
Descripción Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
TDA5360
Pre–Amplifier for Hard Disk Drive with
MR-Read / Inductive Write Heads
Objective specification, Revision 2.2
1998 Jul 30
Philips
Semiconductors

1 page




TDA5360 pdf
Philips Semiconductors
Pre-Amplifier for Hard Disk Drive with
MR-Read / Inductive Write Heads
Objective Specification, Revision 2.2
TDA5360
4 DESCRIPTION
The +/- 5.0 volt pre-amplifier for HDD described here has been designed for 12 terminals, comprised of a SAL or GMR
magneto-resistive reader and an inductive thin film writer. In read mode, the device operates as a low noise differential
preamplifier which senses resistance changes in the MR element that correspond to flux changes on the disk. In write
mode, the circuit operates as a thin film head current switch, driving the inductive element of the head.
The IC incorporates Read amplifiers with programmable gain and HF boosts, Write amplifiers, 3-wires Serial Interface,
Digital-to-Analog Converters, Thermal Asperity Detector and Programmable Thermal Asperity Compressor, reference
and control circuits which operate on a Dual Supply Voltage of +/-5V (+/-10%).
The Read amplifier has programmable medium input impedance. The DC offset between the two terminals of the MR
head is eliminated using on chip AC coupling. The bandwidth can be enhanced by using programmable high frequency
gain-boost. Fast settling features are used to keep the transients short. As an option, the Read amplifier may be left
biased during writing, so as to reduce the duration of these transients even further.
The Write amplifier has a programmable current overshoot which may be added to the programmable steady state write
current.
Fault protection is provided for a variety of read or write unsafe conditions. For added data protection, internal pull up
resistors are connected to RWN, CS0, CS1, STWN, WDP and WDN pins and pull down resistors are connected to SEN,
SDATA, SCLK, DRN and BFAST pins, to prevent accidental writing due to open lines and to ensure the device will power
up in a non-writing condition.
On-chip Digital to Analog converters for MR bias current or power and Write current are programmed via a 3 wire Serial
Interface. Head selection, Mode control, Testing and Servo Writing can also be programmed using the serial interface.
In Sleep mode, the CMOS serial interface is operationnal. Fig 2 shows the block diagram of the IC. Invalid head select
codes disable the writer, select the dummy head and trigger the FLT output.
5 ORDERING INFORMATION
EXTENDED TYPE NUMBER
TDA5360UH
TDA5360UK
PACKAGE
bare die
bumped die
Fig.1 Type Number
1998 July 30
5

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TDA5360 arduino
Philips Semiconductors
Pre-Amplifier for Hard Disk Drive with
MR-Read / Inductive Write Heads
Objective Specification, Revision 2.2
TDA5360
9.5 SLEEP mode
The sleep mode is selected by programming bits MODE0 and MODE1. (see Reg.09)
In Sleep Mode, the IC is accessible via the Serial Interface. All circuits, other than those of the CMOS Serial Interface
and the circuit which forces the data registers to their default values at power up and which fixes the DC level of RDp-
RDn (required when operating with more than one amplifier), are inactive. Typical static current consumption is less than
one mA, depending on the state of the logic pins where internal pull-up or pull-down resistors are connected. Dynamic
current consumption during operation of the Serial Interface in the Sleep mode and owing to external activity at the inputs
to the Serial Interface is not included. In all Modes including the Sleep mode, data registers can be
programmed. Sleep is the default Mode at power-up. Switching to other modes takes less than 0.1 ms.
The CMM of RDP and RDN is the same as in Standby or Active mode. (see Note)
Internal fault detectors are powered off.
Note 1 : At power-up, as long as DRN pin is LOW, a reset of the Serial Interface registers occurs. Before any register
programmation, the user should first force DRN pin to HIGH in order to exit the reset mode and enable a register
programmation. See description of DRN function in (10.6).
Note 2 : As a goal, the CMM of RDP and RDN is identical in all operating modes. The term “high-impedance” here means
at least 10 to 20 kOhm from RDP or RDN to an internal CMM voltage reference.
1998 July 30
11

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