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PDF TDA5153 Data sheet ( Hoja de datos )

Número de pieza TDA5153
Descripción Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
DATA SHEET
TDA5153
Pre-amplifier for Hard Disk Drive
(HDD) with MR-read/inductive write
heads
Preliminary specification
File under Integrated Circuits, IC11
1997 Jul 02

1 page




TDA5153 pdf
Philips Semiconductors
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
Preliminary specification
TDA5153
6 BLOCK DIAGRAM
handbook, full pagewidth
WDlx
WDly
IWDlx(1)
IWDly(1)
2
3
VCC
11
TDA5153
WRITE DRIVER
INPUT
FF
VCC(WD)
(5 to 8 V)
48
15(2), 20, 26,
6(3) 33, 39, 44(2)
6(3) 14(2), 19, 25,
32, 38, 43(2)
nWy
nWx
1
HUS
HEAD UNSAFE
INDICATOR
12
Rext
LOW SUPPLY
VOLTAGE
INDICATOR
WRITE
CURRENT
SOURCE
6(3)
VOLTAGE
REFERENCE
WRITE DRIVER
AND
READ PREAMP
(6×)(3)
R/W
SCLK
SEN
SDATA
4
7
5
6
+VCC
SERIAL
INTERFACE
20 k
TAS
DETECTOR
4
head select
5
3
6(3)
RDx
RDy
9
10
RMR
5 CURRENT
SOURCE
4
4
8, 13
GND n
18(2), 23, 29,
6(3) 36, 42, 47(2)
17(2), 22, 28,
6(3) 35, 41, 46(2)
16(2), 21, 27,
6(3) 34, 40, 45(2)
nRy
nGND
nRx
MGK422
Pin numbers correspond to TDA5153AG and TDA5153BG only. See Fig.3 and Chapter 7 for pinning of TDA5153X.
(1) Only available on naked die.
(2) Absent on TDA5153BG (4 channel version).
(3) 4 on TDA5153BG.
Fig.1 Block diagram.
1997 Jul 02
5

5 Page





TDA5153 arduino
Philips Semiconductors
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
Preliminary specification
TDA5153
8.4 Standby mode
The circuit can be put in standby mode using the serial
interface. In standby mode, typical DC current
consumption is 330 µA. Transients from standby mode to
active mode are two orders of magnitude shorter than from
sleep mode to active mode. This is important in the case
of cylinder mode operation with multiple amplifiers.
All amplifiers can operate from standby mode and all head
switch times can be kept just as short as in the case of
operation with a single amplifier. Head switching times are
summarized in the switching characteristics.
8.5 Active mode
Active mode is either read mode or write mode depending
on the R/W pin.
8.6 Bi-directional serial interface
The serial interface is used for programming of the device
and for reading of status information. 16 bits (8 bits for
data and 8 for address) are used to program the device.
The serial interface requires 3 pins: SDATA, SCLK and
SEN. These pins (and R/W) are CMOS inputs. The logic
input R/W has an internal 20 kpull-up resistor and the
SEN logic input has an internal 20 kpull-down resistor.
Thus, in case the SEN line is opened, no data will be
registered and in case the R/W line is opened, the device
will never be in write mode.
SDATA: serial data; bi-directional data interface. In all
circumstances, the LSB is transmitted first.
SCLK: serial clock; 25 MHz clock frequency.
SEN: serial enable; data transfer takes place when SEN is
HIGH. When SEN is LOW, data and clock signals are
prohibited from entering the circuit.
Three phases in the communication are distinguishable:
addressing, programming and reading. Each
communication sequence starts with an addressing
phase, followed by either a programming phase or a
reading phase.
8.7 Addressing
When SEN goes HIGH, bits are latched in at rising edges
of SCLK. The first eight bits a7 to a0, starting with a0, are
shifted serially into an address register. If SEN goes LOW
before 16 bits have been received, the operation is
ignored. When more than 16 bits (address and data) are
latched in before SEN goes LOW, the first 8 bits are
interpreted as an address and the last 8 bits as data.
SEN should go HIGH at least 5 ns before the first rising
edge of SCLK. Data should be valid at least 5 ns before
and after a rising edge of SCLK. The bits a7 to a4
constitute the register address.To validate the
communication with the preamplifier, bits a1, a2 and a3
have to be programmed as (1, 0, 0).
If bit a0 = logic 0, a programming sequence starts.
If bit a0 = logic 1, reading data from the pre-amplifier can
start.
8.8 Programming data
If a0 = logic 0, the last eight bits d7 to d0 before SEN goes
LOW are shifted into an input register. Bits d6 and d7 are
don’t care. When SEN goes LOW, the communication
sequence is ended and the data in the input register is
copied in parallel to the data register that corresponds to
the decoded address a7 to a4. SEN should go LOW at
least 5 ns after the last rising edge of SCLK.
8.9 Reading data
Immediately after the IC detects that a0 = logic 1, data
from the data register (address a7 to a4) is copied in
parallel to the input register. Two wait clock cycles must
follow before the controller can start inputting data. At the
first falling edge of SCLK after the 2 wait rising edges of
SCLK, the LSB d0 is placed on SDATA line followed by d1
at the next falling edge of SCLK etc. If SEN goes LOW
before 8 address bits (a7 to a0) have been detected, the
communication is ignored.
1997 Jul 02
11

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