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PDF TDA4885 Data sheet ( Hoja de datos )
| Número de pieza | TDA4885 | |
| Descripción | 150 MHz video controller with I2C-bus | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA4885
150 MHz video controller with
I2C-bus
Product specification
Supersedes data of 1997 Mar 19
File under Integrated Circuits, IC02
1997 Nov 25
1 page  
Philips Semiconductors
150 MHz video controller with I2C-bus
5 BLOCK DIAGRAM
Product specification
TDA4885
ok, full pagewidth
1997 Nov 25
5
5 Page 
Philips Semiconductors
150 MHz video controller with I2C-bus
Product specification
TDA4885
10 CHARACTERISTICS
All voltages and currents are measured in test circuit of Fig.19; all voltages are measured with respect to GND (pins 9,
28, 23 and 18); VP = VP1, 2, 3 = 8 V (pins 7, 29, 24 and 19); Tamb = 25 °C; nominal input signals [0.7 V (peak-to-peak
value) at pins 6, 8 and 10]; nominal colour signals at signal outputs (pins 30, 25 and 20); reference black level (Vrbl)
approximately 0.7 V; nominal settings for brightness and contrast; maximum settings for OSD contrast and gain; no
limiting of contrast (V17 = 5 V); no OSD fast blanking (pin 1 connected to ground); no gain modulation (pins 12, 13
and 14 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supply
VP
IP
VP1, 2, 3
IP1, 2, 3
VPSO
supply voltage (pin 7)
supply current (pin 7)
note 4
channel supply voltage
(pins 29, 24 and 19)
channel supply current
(pins 29, 24 and 19)
supply voltage for signal switch
off (threshold at pin 7)
signal outputs (pins 30, 25
and 20) open-circuit;
Vrbl = 0.7 V; note 5
signal outputs switched to
switch-off voltage; note 1
7.6 8.0 8.8
− 20 25
7.6 8.0 8.8
− 40 45
− − 7.2
V
mA
V
mA
V
Clamping and blanking pulses (pins 5 and 11)
V5
input clamping and vertical
note 6
blanking input signal
no blanking, no input
−0.1
clamping
blanking, no input clamping 1.6
input clamping, no blanking 3.5
I5 input current
V5 = 1 V; note 7
pin 5 grounded; note 7
−1.5
−80
V5 = −0.1 V; note 7
−250
tr/f5 rise/fall time for input clamping note 6; see Fig.7
pulse, disable for blanking
−
tW5 width of input clamping pulse
0.6
tdl5 delay between leading edges V11 < 0.8 V; input pulse with −
of vertical blanking input pulse 50 ns/V; threshold for rising
and internal blanking pulse
input pulse V5 = 1.4 V;
threshold after input clamping
pulse V5 = 3 V; see Fig.7
tdt5 delay between trailing edges of V11 < 0.8 V; input pulse with −
vertical blanking input pulse 50 ns/V; threshold V5 = 1.4 V;
and internal blanking pulse
see Fig.7
V11 output clamping and blanking note 8
input signal
no blanking, no output
−0.1
clamping
blanking, no output clamping 2.0
blanking, output clamping 3.5
− +1.2
−
−
−0.2
−60
−200
−
2.6
VP
−0.05
−30
−100
75
−−
270 −
115 −
− +0.8
− 2.6
− VP
V
V
V
µA
µA
µA
ns/V
µs
ns
ns
V
V
V
1997 Nov 25
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA4885.PDF ] | |
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