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PDF TDA4858 Data sheet ( Hoja de datos )
| Número de pieza | TDA4858 | |
| Descripción | Economy Autosync Deflection Controller (EASDC) | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA4858
Economy Autosync Deflection
Controller (EASDC)
Product specification
Supersedes data of 1996 Jul 18
File under Integrated Circuits, IC02
1997 Oct 27
1 page  
Philips Semiconductors
Economy Autosync Deflection Controller
(EASDC)
Product specification
TDA4858
PINNING
SYMBOL PIN
DESCRIPTION
HFLB
1 horizontal flyback input
XRAY
2 X-ray protection input
BOP
3 B+ control OTA output;
comparator input
BSENS 4 B+ control comparator input/output
BIN 5 B+ control OTA input
BDRV
6 B+ control driver output
HDRV
7 horizontal driver output
PGND
8 power ground
VCC
CLSEL
9 supply voltage
10 selection input for horizontal clamping
trigger
EWDRV 11 EW parabola output
VOUT2 12 vertical output 2 (ascending sawtooth)
VOUT1
13 vertical output 1 (descending
sawtooth)
VSYNC
14 vertical synchronization input/output
(TTL level)
HSYNC 15 horizontal/composite synchronization
input (TTL level or sync-on-video)
CLBL
16 video clamping pulse/vertical blanking
and protection output
VPOS
17 vertical shift input
VAMP
18 vertical size input
VSCOR 19 vertical S-correction input
EWTRP 20 EW trapezium correction input
EWPAR 21 EW parabola amplitude input
VAGC
22 external capacitor for vertical
amplitude control
VREF
23 external resistor for vertical oscillator
VCAP
24 external capacitor for vertical oscillator
SGND
25 signal ground
HPLL1 26 external filter for PLL1
HBUF
27 buffered f/v voltage output
HREF
28 reference current for horizontal
oscillator
HCAP
29 external capacitor for horizontal
oscillator
HPOS
30 horizontal shift input
HPLL2 31 external filter for PLL2/soft start
EWWID 32 horizontal size input
handbook, halfpage
HFLB 1
XRAY 2
32 EWWID
31 HPLL2
BOP 3
30 HPOS
BSENS 4
BIN 5
BDRV 6
HDRV 7
29 HCAP
28 HREF
27 HBUF
26 HPLL1
PGND 8
VCC 9
25 SGND
TDA4858
24 VCAP
CLSEL 10
23 VREF
EWDRV 11
22 VAGC
VOUT2 12
VOUT1 13
VSYNC 14
HSYNC 15
21 EWPAR
20 EWTRP
19 VSCOR
18 VAMP
CLBL 16
17 VPOS
MGD095
Fig.2 Pin configuration.
1997 Oct 27
5
5 Page 
Philips Semiconductors
Economy Autosync Deflection Controller
(EASDC)
Product specification
TDA4858
Supply voltage stabilizer, references and protection
The EASDC provides an internal supply voltage stabilizer
for excellent stabilization of all internal references.
An internal gap reference especially designed for
low-noise is the reference for the internal horizontal and
vertical supply voltages. All internal reference currents and
drive current for the vertical output stage are derived from
this voltage via external resistors.
A special protection mode has been implemented in order
to protect the deflection stages and the picture tube during
start-up, shut-down and fault conditions. This protection
mode can be activated as shown in Table 3.
Table 3 Activation of protection mode
ACTIVATION
Low supply voltage at pin 9
X-ray protection XRAY (pin 2)
triggered
HPLL2 (pin 31) pulled to
ground
RESET
increase supply voltage
remove supply voltage
release pin 31
When protection mode is active, several pins of the ASDC
are forced into a defined state:
HDRV (horizontal driver output) is floating
BDRV (B+ control driver output) is floating
VOUT1 and VOUT2 (vertical outputs) are floating
CLBL provides a continuous blanking signal
The capacitor at HPLL2 is discharged.
If the protection mode is activated via the supply voltage at
pin 9, all these actions will be performed in a well defined
sequence (see Fig.14). For activation via X-ray protection
or HPLL2 all actions will occur simultaneously.
The return to normal operation is performed in accordance
with the start-up sequence in Fig.14a, if the reset was
caused by the supply voltage at pin 9. The first action with
increasing supply voltage is the activation of continuous
blanking at CLBL. When the threshold for activation of
HDRV is passed, an internal current begins to charge the
external capacitor at HPLL2 and a PLL2 soft start
sequence is performed (see Fig.15). In the beginning of
this phase the horizontal driver stage generates very small
output pulses. The width of these pulses increases with the
voltage at HPLL2 until the final duty cycle is reached. Then
the PLL2 voltage passes the threshold for activation of
BDRV, VOUT1 and VOUT2.
For activation of these pins not only the PLL2 voltage, but
also the supply voltage must have passed the appropriate
threshold. A last pair of thresholds has to be passed by
PLL2 voltage and supply voltage before the continuous
blanking is finally removed, and the operation of PLL2 and
frequency-locked loop is enabled.
A return to the normal operation by releasing the voltage
at HPLL2 will lead to a slightly different sequence. Here the
activation of all functions is influenced only by the voltage
at HPLL2 (see Fig.15).
Application hint: Internal discharge of the capacitor at
HPLL2 will only be performed, if the protection mode was
activated via the supply voltage or X-ray protection.
1997 Oct 27
11
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet TDA4858.PDF ] | |
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