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PDF TDA4856 Data sheet ( Hoja de datos )
| Número de pieza | TDA4856 | |
| Descripción | I2C-bus autosync deflection controller for PC monitors | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA4856
I2C-bus autosync deflection
controller for PC monitors
Product specification
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC02
1999 Jul 13
1 page  
Philips Semiconductors
I2C-bus autosync deflection controller for
PC monitors
Product specification
TDA4856
PINNING
SYMBOL
HFLB
XRAY
BOP
BSENS
BIN
BDRV
PGND
HDRV
XSEL
VCC
EWDRV
VOUT2
VOUT1
VSYNC
HSYNC
CLBL
HUNLOCK
SCL
SDA
ASCOR
VSMOD
VAGC
VREF
VCAP
SGND
HPLL1
HBUF
HREF
HCAP
HPLL2
HSMOD
FOCUS
PIN DESCRIPTION
1 horizontal flyback input
2 X-ray protection input
3 B+ control OTA output
4 B+ control comparator input
5 B+ control OTA input
6 B+ control driver output
7 power ground
8 horizontal driver output
9 select input for X-ray reset
10 supply voltage
11 EW waveform output
12 vertical output 2 (ascending sawtooth)
13 vertical output 1 (descending sawtooth)
14 vertical synchronization input
15 horizontal/composite synchronization input
16 video clamping pulse/vertical blanking output
17 horizontal synchronization unlock/protection/vertical blanking output
18 I2C-bus clock input
19 I2C-bus data input/output
20 output for asymmetric EW corrections
21 input for EHT compensation (via vertical size)
22 external capacitor for vertical amplitude control
23 external resistor for vertical oscillator
24 external capacitor for vertical oscillator
25 signal ground
26 external filter for PLL1
27 buffered f/v voltage output
28 reference current for horizontal oscillator
29 external capacitor for horizontal oscillator
30 external filter for PLL2/soft start
31 input for EHT compensation (via horizontal size)
32 output for horizontal and vertical focus
1999 Jul 13
5
5 Page 
Philips Semiconductors
I2C-bus autosync deflection controller for
PC monitors
Product specification
TDA4856
Two different modes of operation can be chosen for the
EW output waveform via control bit FHMULT:
1. Mode 1
Horizontal size is controlled via register HSIZE and
causes a DC shift at the EWDRV output. The complete
waveform is also multiplied internally by a signal
proportional to the line frequency [which is detected
via the current at HREF (pin 28)]. This mode is to be
used for driving EW diode modulator stages which
require a voltage proportional to the line frequency.
2. Mode 2
The EW drive waveform does not track with the line
frequency. This mode is to be used for driving EW
modulators which require a voltage independent of the
line frequency.
Output stage for asymmetric correction waveforms
[ASCOR (pin 20)]
This output is designed as a voltage output for
superimposed waveforms of vertical parabola and
sawtooth. The amplitude and polarity of both signals can
be changed by registers HPARAL and HPINBAL via the
I2C-bus.
Application hint: The TDA4856 offers two possibilities to
control registers HPINBAL and HPARAL.
1. Control bit ACD = 1
The two registers now control the horizontal phase by
means of internal modulation of the PLL2 horizontal
phase control. The ASCOR output (pin 20) can be left
unused, but it will always provide an output signal
because the ASCOR output stage is not influenced by
the control bit ACD.
2. Control bit ACD = 0
The internal modulation via PLL2 is disconnected.
In order to obtain the required effect on the screen,
pin ASCOR must now be fed to the DC amplifier which
controls the DC shift of the horizontal deflection. This
option is useful for applications which already use a
DC shift transformer.
If the tube does not need HPINBAL and HPARAL, then
pin ASCOR can be used for other purposes, i.e. for a
simple dynamic convergence.
Dynamic focus section [FOCUS (pin 32)]
This section generates a complete drive signal for dynamic
focus applications. The amplitude of the horizontal
parabola is internally stabilized, thus it is independent of
the horizontal frequency. The amplitude can be adjusted
via register HFOCUS. Changing horizontal size may
require a correction of HFOCUS. To compensate for the
delay in external focus amplifiers a ‘pre-correction’ for the
phase of the horizontal parabola has been implemented
(see Fig.28). The amount of this pre-correction can be
adjusted via register HFOCAD. The amplitude of the
vertical parabola is independent of frequency and tracks
with all vertical adjustments. The amplitude can be
adjusted via register VFOCUS.
FOCUS (pin 32) is designed as a voltage output for the
superimposed vertical and horizontal parabolas.
B+ control function block
The B+ control function block of the TDA4856 consists of
an Operational Transconductance Amplifier (OTA), a
voltage comparator, a flip-flop and a discharge circuit. This
configuration allows easy applications for different B+
control concepts. See also Application Note AN96052:
“B+ converter Topologies for Horizontal Deflection and
EHT with TDA4855/58”.
GENERAL DESCRIPTION
The non-inverting input of the OTA is connected internally
to a high precision reference voltage. The inverting input is
connected to BIN (pin 5). An internal clamping circuit limits
the maximum positive output voltage of the OTA.
The output itself is connected to BOP (pin 3) and to the
inverting input of the voltage comparator.
The non-inverting input of the voltage comparator can be
accessed via BSENS (pin 4).
B+ drive pulses are generated by an internal flip-flop and
fed to BDRV (pin 6) via an open-collector output stage.
This flip-flop is set at the rising edge of the signal at HDRV
(pin 8). The falling edge of the output signal at BDRV has
a defined delay of td(BDRV) to the rising edge of the HDRV
pulse. When the voltage at BSENS exceeds the voltage at
BOP, the voltage comparator output resets the flip-flop
and, therefore, the open-collector stage at BDRV is
floating again.
1999 Jul 13
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA4856.PDF ] | |
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