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PDF TDA4455 Data sheet ( Hoja de datos )
| Número de pieza | TDA4455 | |
| Descripción | Multistandard VIF Amplifier and PLL Demodulator | |
| Fabricantes | TEMIC Semiconductors | |
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TELEFUNKEN Semiconductors
TDA4455
Multistandard VIF Amplifier and PLL Demodulator
Application
Monolithic integrated circuit for vision IF signal processing in multistandard TV and VTR sets.
Description
This multistandard video IF processing circuit with PLL
picture carrier regeneration gives a high performance of
linear video demodulation.
With two IF inputs (Pins 1–2 and Pins 17–18), it is
possible to select between two signal sources. The input
selector switch (Pin 16) works independent from the
standard switch (Pin 11).
The IF signal is internally fed via a 3-stage controlled
wideband amplifier to the video demodulator and the
phase detector. The phase detector compares the phase of
IF signal (0°) with the output signal of the VCO (90°) and
sets the VCO frequency accordingly. A lock detector
switches the PLL loop filter according to the state of the
PLL (locked-PLL slow, unlocked-PLL fast).
A second output of the VCO (0°) provides the reference
carrier for the video demodulator. The polarity of the
demodulator can be inverted by the standard switch
(Pin 11), so that negative or positive modulated IF signals
are always available with the same polarity at the demo-
dulator output. The demodulated video signal is filtered,
amplified and fed via an interference limiter to the video
output (Pin 7).
The standard switch also determines the clamp level of
the video amplifier and the required IF-AGC mode. In the
standard B/G mode the sync peak value is the criterion for
a fast charge and discharge. In the standard L mode on the
other hand, fast AGC action is achieved by charging at
peak white level and discharging by the averaged video
signal (time constant on Pin 8). The response level for
discharge has a hysteresis. In the D2MAC mode a similar
function is applied to achieve the AGC, but with different
threshold levels.
An overload detector prevents the PLL becoming
unlocked by large IF input signals.
To achieve a delayed tuner-AGC action, the current out-
put (Pin 4) can be adjusted with a resistor at Pin 3.
Features
D Suitable for standard B/G, L and D2MAC, processes
negative and positive modulated IF-signals with equal
polarity of the output signal
D Two IF-inputs, for switching between two signal
sources (e.g., two tuners and two SAW-filters)
D High performance video demodulator with PLL
picture carrier regeneration
D Extended video bandwidth (12 MHz) for the demodu-
lation of amplitude modulated MAC-signals
D Standard B/G: AGC acting on the sync peak pulse
D Standard L: fast AGC acting on peak white level with
average value controlled capacitor discharge and
reference hysteresis
D D2MAC: fast AGC acting on peak level with
controlled capacitor discharge
D Output for delayed tuner-AGC, take over point
adjustable
D High input sensitivity
D Ultra white and ultra black limiting
D Supply voltage range 6.8 to 13 V
D Low power consumption
D ESD protection
Package Options
Case: 18-pin DIL plastic
Rev. A1: 08.05.1995
Preliminary Information
1 (12)
1 page  
TELEFUNKEN Semiconductors
TDA4455
Parameters
Test Conditions / Pins Symbol Min. Typ. Max. Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁIF residual voltage
f = 38.9 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁf = 77.8 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁUpsetting factor of sync
Vres1
Vres2
DVsync
2
5
3
mV
mV
%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁpulse in the AGC range
Vsync
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTilt of half picture
between black and white
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁUltra black limiting
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁthreshold
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁUltra white limiting
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁthreshold
Standard L
Below sync level
Above ultra white level
DVlim1
DVlim2
5 10 %
250 mV
500 mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁStandard switch
Pin 11
Control voltage B/G
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁControl voltage L
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁControl voltage D2MAC
Note 6
Vsw1
Vsw2
Vsw3
2.5
0
5.0
4.0 V
1.5 V
Vs V
Input selector switch
Pin 16
Control voltage – input 1
active
Note 7
5.0 VS V
Control voltage – input 2
0 2.5 V
active
Notes
1. A peak white value for at least 10 µs must be trans-
mitted for each complete frame
2. Loop filter: R1 = 500 W – 1 k, C1 = 0.47 mF
Capacitor VCO circuit: CVCO = 27 – 47 pF
3. Pin 7 unloaded
4. Residual carrier: 10% carrier amplitude
5. Blanking level: 30% carrier amplitude
6. Without control voltage at Pin 11 – standard B/G is
automatically selected
7. Without control voltage at Pin 16 – input 1 is auto-
matically active
Alignment of the VCO
1. Apply 4.5 V to Pin 6, to disable the broadband
amplifier.
2. Measure the dc-voltage at Pin 12 (phase detector).
3. Apply a 38.9 MHz unmodulated carrier signal to the
IF input (Pins 1–2 or Pins 17–18); adjust the input
level so that the AGC voltage at Pin 6 is between
2.0 V and 2.5 V.
4. Adjust the VCO circuit until at Pin 12 is the same DC-
voltage as measured in step 2.
Rev. A1: 08.05.1995
Preliminary Information
5 (12)
5 Page 
TELEFUNKEN Semiconductors
Dimensions in mm
Package: DIP 16
TDA4455
94 9128
Rev. A1: 08.05.1995
Preliminary Information
11 (12)
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet TDA4455.PDF ] | |
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