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PDF TDA16888G Data sheet ( Hoja de datos )
| Número de pieza | TDA16888G | |
| Descripción | High Performance Power Combi Controller | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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High Performance Power Combi Controller
TDA 16888
1 Overview
1.1 Features
PFC Section
– IEC 1000-3 compliant
– Additional operation mode as auxiliary power supply
– Fast, soft switching totem pole gate drive (1 A)
– Dual loop control (average current and voltage
sensing)
– Leading edge triggered pulse width modulation
– Peak current limitation
– Topologies of PFC preconverter are boost or flyback
– Continuous/discontinuous mode possible
– 94% maximum duty cycle
P-DIP-20-5
P-DSO-20-1
PWM Section
– Improved current mode control
– Fast, soft switching totem pole gate drive (1 A)
– Soft-start management
– Trailing edge triggered pulse width modulation
– Topologies of PWM converter are feed forward or flyback
– 50% maximum duty cycle to prevent transformer saturation
– fPWM = fPFC
Type
w TDA 16888
w TDA 16888G
w New type
Ordering Code
Q67000-A9284-X201-K5
Q67000-A9310-A702
Package
P-DIP-20-5
P-DSO-20-1
Semiconductor Group
1 Data Sheet 1998-05-06
1 page  
1.4 Block Diagram
TDA 16888
1
Figure 2
Semiconductor Group
5 Data Sheet 1998-05-06
5 Page 
TDA 16888
The oscillator can be synchronized with an external clock signal supplied at pin 12
(SYNC). As long as this clock signal is H the oscillator’s triangular signal VOSC is
interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However,
as soon as the external clock changes from H to L the oscillator is released.
Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the
oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on
principle only within the range from 0.66 fOSC to 2 fOSC. Please note, that the slope of the
falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead
the lower voltage peak is modulated. Consequently, on the one hand at high
synchronization frequencies fSYNC > fOSC the amplitude of the ramp signal and
correspondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand
at low synchronization frequencies fSYNC < fOSC the lower voltage peak is clamped to the
minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which
may cause undefined PFC duty cycles as the voltage VPFC CC at pin 3 (PFC CC) drops
below this threshold. However, if the oscillator has to be synchronized over a wide
frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has
to be preferred to a synchronization by means of pin 12 (SYNC).
In order to reduce the overall current consumption under low load conditions, the
oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less
than 0.4 V (disabled PWM section).
Multiplier
The multiplier serves to provide the controlled current IQM by combination of the shape
of the sinusoidal input current IM1 derived from the voltage at pin 1 (PFC IAC) by means
of the 10 kΩ resistor R2, the magnitude of the PFC output voltage VM2 given at pin 18
(PFC VC) and the possibility for soft overvoltage protection VM3 (see Chapter
Protection Circuitry). By means of this current the required power factor as well as the
magnitude of the PFC output voltage is ensured. To achieve an excellent performance
over a wide range of output power and input voltage, the input voltage VM2 is amplified
by an exponential function before being fed into the multiplier (see Figure 8).
Voltage Amplifier OP1
Being part of the outer loop the error amplifier OP1 controls the magnitude of the PFC
output voltage by comparison of the PFC output voltage measured at pin 17 (PFC FB)
with an internal reference voltage. The latter is fixed to 5 V in order to achieve immunity
from external noise. To allow for individual feedback the output of OP1 is connected to
pin 18 (PFC VC).
Semiconductor Group
11 Data Sheet 1998-05-06
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA16888G.PDF ] | |
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