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Número de pieza TDA1547
Descripción Dual top-performance bitstream DAC
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
TDA1547
Dual top-performance bitstream
DAC
Product specification
File under Integrated Circuits, IC01
September 1991

1 page




TDA1547 pdf
Philips Semiconductors
Dual top-performance bitstream DAC
Product specification
TDA1547
SYMBOL
CLK L
n.c.
IN L
VSSD
VSUB
PIN
28
29
30
31
32
DESCRIPTION
clock input for the left channel
pin not connected; should preferably be connected to digital ground
serial one-bit data input for the left channel
5 V digital supply for both channels
5 V substrate voltage
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITION
Supply voltages
VDDD L. R
positive digital supply voltage for one
channel; pins 27 and 6
VDDD
digital supply voltage for both channels;
pin 2
VSSD L. R
negative digital supply voltage for one
channel; pins 26 and 7
VSSD
negative digital supply voltage for both
channels; pin 31
VDDA
VSSA
positive analog supply voltage; pin 17
negative analog supply voltage; pin 16
Supply current
IDDD L. R
positive digital supply current for one
channel; pins 27 and 6
IDDD digital supply current for both channels;
pin 2
ISSD L. R
negative digital supply current for one
channel; pins 26 and 7
ISSD negative supply current for both channels;
pin 31
IDDA
ISSA
Ptot
VOUT(RMS)
positive analog supply current; pin 17
negative analog supply current; pin 16
total power dissipation
output voltage (RMS value)
fCLK = 8.46 MHz;
notes 1 and 2
MIN TYP MAX UNIT
4.5 5.0 5.5 V
4.5 5.0 5.5 V
4.0 3.5 3.0 V
5.5 5.0 4.5 V
4.5 5.0 6
V
6.0 5.0 4.5 V
0.1 mA
29.0 mA
− −0.1 mA
− −28.0 mA
51.0 mA
− −51.0 mA
800 mW
0.85 1.0 1.15 V
September 1991
5

5 Page





TDA1547 arduino
Philips Semiconductors
Dual top-performance bitstream DAC
Product specification
TDA1547
Notes to the characteristics
1. The substrate voltage must be lower than or to equal than the lowest supply voltage.
2. Output level tracks linearly with both the clock frequency and the reference voltage (Vref L or Vref R).
3. Device measured in differential mode with external components as shown in Fig.5.
4. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 1 kHz digital
sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
5. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 20 Hz to 20 kHz
digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
6. Power supply rejection ratio measured with fripple = 1 kHz and vripple = 100 mV.
7. The specified signal-to-noise ratio includes noise introduced by the application components as shown in Fig.5.
TIMING
handbook, full pagewidth
tr
CLK
t CLK H
VIH
t f t CLK L
VDDD – 1.0 V
1.0 V VIL
DATA INPUT
CHANNEL L,
CHANNEL R
VIH
V IL
t SU t HD
DATA STABLE
V IL
Fig.3 Timing waveform.
VDDD – 1.0 V
1.0 V
MCD295
September 1991
11

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