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PDF TDA10045H Data sheet ( Hoja de datos )
| Número de pieza | TDA10045H | |
| Descripción | DVB-T channel receiver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA10045H
DVB-T channel receiver
Product specification
Supersedes data of 2000 Jun 21
File under Integrated Circuits, IC02
2001 Nov 08
1 page  
Philips Semiconductors
DVB-T channel receiver
Product specification
TDA10045H
PINNING
SYMBOL
VDDD33
VSSD
DS_SPARE3
VAGC
SCL_EEP
VDDD33
VSSD
SDA_EEP
PIN
1
2
3
4
5
6
7
8
SCL_TUN
9
SDA_TUN
10
SCL
SDA
n.c.
CLR#
EEPADDR
11
12
13
14
15
SADDR[1:0] 16 and 17
VDDD18
VSSD
TM[3:0]
SCAN_EN
VDDD50
VSSD
DWNLOAD
18
19
20 to 23
24
25
26
27
SP_IN[1:0] 28 and 29
TYPE
−
−
O
O
O
−
−
I/OD
OD(1)
I/OD
I(2)
I/OD
−
I(2)
I(2)
I(2)
−
−
I(2)
I(2)
−
−
I(2)
I(2)
DESCRIPTION
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V
spare delta-sigma output; managed by the DSP to generate an analog level
(after a RC low-pass filter)
output value from the Delta-Sigma modulator, used to control a log-scaled
amplifier (after analog filtering)
extra I2C-bus clock to download DSP code from an external EEPROM (optional
mode); can be connected to the master I2C-bus
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V)
extra I2C-bus data bus to download DSP code from an external EEPROM
(optional mode). It can be connected to the master I2C-bus; this pin is
open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used.
tuner I2C-bus serial clock signal; this signal is derived from the master SCL and
is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used
tuner I2C-bus serial data signal; this signal is derived from the master SDA and
is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used
I2C-bus master serial clock; up to 700 kbit/s
I2C-bus master serial data input/output, open-drain I/O pad, which requires an
external pull-up resistor (to VDDD33 or VDDD50)
not connected
asynchronous reset signal; active LOW
EEPADDR is the LSB of the I2C-bus address of the EEPROM. The MSBs are
internally set to 101000. Therefore the complete I2C-bus address of the
EEPROM is (MSB to LSB): 1, 0, 1, 0, 0, 0, EEPADDR.
SADDR[1:0] are the 2 LSBs of the I2C-bus address of the TDA10045; the MSBs
are internally set to 00010; therefore the complete I2C-bus address of the
TDA10045 is (MSB to LSB): 0, 0, 0, 1, 0, SADDR[1] and SADDR[0]
digital supply voltage for the core (1.8 V typ.)
digital ground supply (0 V)
test mode bus; for test purpose; must be set to ‘0000’
scan enable for production test; connected to GND
digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if the 5 V
tolerant I/O is not required
digital ground supply (0 V)
processor control, boot mode; if set to logic 0, the DSP downloads the software
from an external EEPROM on the dedicated I2C-bus (pins SDA_EEP and
SCL_EEP). If set to logic 1 the software is downloaded in the I2C-bus register
CODE_IN from the host; in this case the external EEPROM is not needed.
spare inputs
2001 Nov 08
5
5 Page 
Philips Semiconductors
DVB-T channel receiver
Product specification
TDA10045H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power consumption
IDDD
digital supply current on
fs = 29 Mhz; direct IF
pins:
application
VDDD18 and VDDD1
VDDD33
VCCD(PLL), VDDA2 and VDDA3
VDDD50
Ptot total power dissipation
−
140 160
mA
−
3−
mA
−
35 −
mA
−
5−
mA
−
400 470
mW
Notes
1. The voltage level of the 5 V supply must always exceed, or at least equal, the voltage level of the 3.3 V supply during
power-up and down in order to guarantee protection against latch-up.
2. All inputs are 5 V tolerant.
2001 Nov 08
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet TDA10045H.PDF ] | |
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