PDF TD62C805F Data sheet ( Hoja de datos )

Número de pieza	TD62C805F
Descripción	48BIT THERMAL HEAD DRIVER
Fabricantes	Toshiba
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Hay una vista previa y un enlace de descarga de TD62C805F (archivo pdf) en la parte inferior de esta página. Total 13 Páginas
No Preview Available ! TD62C805F TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TD62C805F 48BIT THERMAL HEAD DRIVER The TD62805F is a general purpose 48bit driver IC consisting of 8 block 8bit shift register and 48bit drivers (Open Drain). This device is best suited as a 48 dot thermal printer head drivers. FEATURES l 8bit parallel input and 6 block 8bit shift register l CMOS compatible input. l High driverability ·········· 30 V / 100 mA / ch l Built in monostable multivibrator for head protection l 16 steps gray scale operating with 4bit data l 48bit open drain outputs l Package ·························· µPFP−80 pin Weight: 1.53 g (Typ.) 1 2001-07-05 1 page TD62C805F (1) Data Input D1~D6 of Input Dates are entered to shift Register by the clock signal with the timing of rise. Outputs are latched by holding the WRITE·CLK “Low” or to stop the clock signal. PWM Data (DATA1~4) are latched by OUT / PWM signal “Low”. (2) Output Enable Outputs become “OFF” at the first rising edge of E·CLK after the OUT·E to “High”, and become “ON” at the first rising edge of E·CLK after the OUT·E to “Low”. Output ON / OFF duty is controlled by controlling OUT·E signal directly or to change the timing of WRITE·E and E·CLK. 5 2001-07-05 5 Page TD62C805F SWITCHING CHARACTERISTICS (VDD = 5.5 V, VDS = 26 V, Ta = 25°C) CHARACTERISTIC SYMBOL TEST CONDITION Maximum Operating Clock Frequency CLK− OUTn , WRITE·CLK− OUTn RESET − OUTn Propagation Delay Time “L”−”H” COUNTER, CLK−OUTn (Note) OUT· E − OUTn , WRITE· E − OUTn E ·CLK− OUTn MMV / E − OUTn CLK− OUTn , WRITE·CLK− OUTn Propagation Delay Time “H”−”L” RESET − OUTn COUNTER, CLK−OUTn (Note) OUT· E − OUTn , WRITE· E − OUTn E ·CLK− OUTn MMV / E − OUTn Minimum Clock Pulse Width DATA−OUT / PWM Data Set Up Time DATA−CLK OUT· E − E ·CLK DATA−OUT / PWM Data Hold Time DATA−CLK OUT· E − E ·CLK Maximum Rise Time COUNTER·CLK CLK Maximum Fall Time COUNTER·CLK CLK Output Rise Time Output Fall Time OUTn MMV Pulse Width fMAX Duty 50% tpLH Duty 50% VIN (H) = 4.5 V VIN (L) = 0 V RL = 375 Ω CL = 15 pF tpHL tw tsetup thold tr tf tor tof tMMV ― ― ― ― ― ― ― Note: COUNTER DATA = F MIN TYP. MAX UNIT 10 ― ― MHz ― 80 ― ― 100 ― ― 110 ― ― 100 ― ― 130 ― ― 60 ― ― 100 ― ― 90 ― ― 70 ― ― 80 ― 25 ― ns ― 10 ― ― 10 ― ―― 1 ― ― 1 µs ― 0.02 1 ― 0.05 0.4 ― 3 ― ms PRECAUTIONS for USING This IC does not integrate protection circuits such as overcurrent and overvoltage protectors. Thus, if excess current or voltage is applied to the IC, the IC may be damaged. Please design the IC so that excess current or voltage will not be applied to the IC. Utmost care is necessary in the design of the output line, VCC and GND line since IC may be destroyed due to short−circuit between outputs, air contamination fault, or fault by improper grounding. 11 2001-07-05 11 Page

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