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PDF TC850IJL Data sheet ( Hoja de datos )

Número de pieza TC850IJL
Descripción 15-BIT/ FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER
Fabricantes TelCom Semiconductor 
Logotipo TelCom Semiconductor Logotipo



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1
TC850
15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL
CONVERTER
2
FEATURES
s 15-bit Resolution Plus Sign Bit
s Up to 40 Conversions per Second
s 12 Conversions per Second Guaranteed
s Integrating ADC Technique
— Monotonic
— High Noise Immunity
— Auto-Zeroed Amplifiers Eliminate Offset
Trimming
s Wide Dynamic Range ...................................... 96dB
s Low Input Bias Current ................................... 30pA
s Low Input Noise ........................................... 30µVP-P
s Sensitivity ....................................................... 100µV
s Flexible Operational Control
— Continuous or On-Demand Conversions
— Data Valid Output
s Bus Compatible, 3-State Data Outputs
— 8-Bit Data Bus
— Simple µP Interface
— Two Chip Enables
— Read ADC Result Like Memory
s ± 5V Power Supply Operation ...................... 20mW
s 40-Pin Dual-in-Line or 44-Pin PLCC Packages
FUNCTIONAL BLOCK DIAGRAM
REF2 +
REF1 +
REF
39 34 36
IN +
IN
COMMON
32
31
30
ANALOG
MUX
A/D
CONTROL
SEQUENCER
RINT
CINT
BUF INT IN
25 24
+
BUFFER
TC850
INT OUT
23
+
INTEGRATOR
CLOCK
OSCILLATOR
÷4
BUS INTERFACE
DECODE LOGIC
17 18 5 7 6 3 4 1 2
–5V +5V
22 40
COMPARATOR
+
6-BIT
9-BIT
UP/DOWN UP/DOWN
COUNTER COUNTER
DATA LATCH
OCTAL 2-INPUT MUX
3-STATE DATA BUS
15 . . . . 8
OSC1
OSC2 CONT/ L/H OVR/ WR RD CS CE
DEMAND
POL
DB0
DB7
TELCOM SEMICONDUCTOR, INC.
GENERAL DESCRIPTION
The TC850 is a monolithic CMOS analog-to-digital
converter (ADC) with resolution of 15-bits plus sign. It
combines a chopper-stabilized buffer and integrator with a
unique multiple-slope integration technique that increases
conversion speed. The result is 16 times improvement in
speed over previous 15-bit, monolithic integrating ADCs
(from 2.5 conversions per sec up to 40 per sec). Faster
conversion speed is especially welcome in systems with
human interface, such as digital scales.
The TC850 incorporates an ADC and a µP-compatible
digital interface. Only a voltage reference and a few noncriti-
cal passive components are required to form a complete 15-
bit plus sign ADC.
CMOS processing provides the TC850 with high-
impedance differential inputs. Input bias current is typically
only 30pA, permitting direct interface to sensors. Input
sensitivity of 100µV per least significant bit (LSB) eliminates
the need for precision external amplifiers. The internal
amplifiers are auto-zeroed, guaranteeing a zero digital output
with 0V analog input. Zero adjustment potentiometers or
calibrations are not required.
The TC850 outputs data on an 8-bit, 3-state bus. Digital
inputs are CMOS compatible; outputs are TTL/CMOS com-
patible. Chip-enable and byte-select inputs combined with
an end-of-conversion output ensures easy interfacing to a
wide variety of microprocessors. Conversions can be per-
formed continuously or on command. In continuous mode,
data is read as three consecutive bytes and manipulation of
address lines is not required.
Operating from ±5V supplies, the TC850 dissipates only
20mW. It is packaged in 40-pin plastic or ceramic dual-in-
line packages (DIPs) and in a 44-pin plastic leaded chip
carrier (PLCC), surface-mount package.
3
4
5
6
ORDERING INFORMATION
Part No.
TC850CLW
TC850CPL
TC850IJL
TC850ILW
Package
Temperature Range
44-Pin PLCC
40-Pin Plastic DIP
40-Pin CerDIP
44-Pin PLCC
0°C to +70°C
0°C to +70°C
– 25°C to +85°C
– 25°C to +85°C
7
TC850-4 11/5/96
3-77
8

1 page




TC850IJL pdf
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
1
TC850
THEORY OF OPERATION
The TC850 is a multiple-slope, integrating analog-to-
digital converter (ADC). The multiple-slope conversion pro-
cess, combined with chopper-stabilized amplifiers, results
in a significant increase in ADC speed, while maintaining
very high resolution and accuracy.
Dual-Slope Conversion Principles
The conventional dual-slope converter measurement
cycle (shown in Figure 2A) has two distinct phases:
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An oppo-
site polarity constant reference voltage is then integrated
until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, complete conversion
requires the integrator output to "ramp-up" and "ramp-
down." Most dual-slope converters add a third phase, auto-
zero. During auto-zero, offset voltages of the input buffer,
integrator, and comparator are nulled, thereby eliminating
the need for zero-offset adjustments.
Dual-slope converter accuracy is unrelated to the inte-
grating resistor and capacitor values, as long as they are
stable during a measurement cycle. By converting the
unknown analog input voltage into an easily-measured
function of time, the dual-slope converter reduces the need
for expensive, precision passive components.
Noise immunity is an inherent benefit of the integrating
conversion method. Noise spikes are integrated, or aver-
aged, to zero during the integration period. Integrating ADCs
are immune to the large conversion errors that plague
successive approximation converters in high-noise environ-
ments.
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
1
RC
tSI
VIN(t) dt =
0
VR tRI ,
RC
where: VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
TELCOM SEMICONDUCTOR, INC.
Multiple-Slope Conversion Principles
One limitation of the dual-slope measurement tech-
nique is conversion speed. In a typical dual-slope method,
the auto-zero and integrate times are each one-half of the
deintegrate time. For a 15-bit conversion, 214 + 214 + 215
(65,536) clock pulses are required for auto-zero, integrate,
and deintegrate phases, respectively. The large number of
clock cycles effectively limits the conversion rate to about
2.5 conversions per second, when a typical analog CMOS
fabrication process is used.
The TC850 uses a multiple-slope conversion technique
to increase conversion speed (Figure 2B). This technique
makes use of a two-slope deintegration phase and permits
15-bit resolution up to 40 conversions per second.
During the TC850's deintegration phase, the integration
capacitor is rapidly discharged to yield a resolution of 9 bits.
At this point, some charge will remain on the capacitor. This
remaining charge is then slowly deintegrated, producing an
+5V –5V
2
3
4
**
**
40 20
22
VDD
16 BUSY
8 DB7
DGND
VSS + 32
IN
IN
31
9 DB6
10 DB5
COMMON 30
+
REF1
39
11 DB4
12 DB3
13 DB2
14 DB1
15 DB0
1 CS
TC850
+
REF2
REF–
CR+ EF1
CR– EF1
CR+ EF2
33
36
38
37
34
2 CE
CR–EF2 35
3 WR
4 RD
BUFFER 25
5 CONT/DEMAND
INTIN 24
6 OVR/POL
7 L/H
INTOUT 23
17
61.44 kHz OSC1
TEST 19
18 OSC2
21 COMP
CINTA CINTBCBUFACBUFB
28 29
27 26
0.1
0.1 0.1
0.1 0.1
µF
µF µF
µF µF
100 M
0.01 µF INPUT
+1.6384V
+0.0265V
1 µF*
1 µF*
120 M
RINT
0.1µF
CINT
NC
5
6
7
NOTES: Unless otherwise specified, all 0.1µF capacitors are film dielectric.
Ceramic capacitors are not recommended.
NC = No internal capacitors
*Polypropylene capacitors.
** 100pF Mica capacitors.
Figure 1. Standard Circuit Configuration
3-81
8

5 Page





TC850IJL arduino
15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
1
TC850
Integration Capacitor
The integration capacitor should be selected to produce
an integrator swing of 4V at full scale. The capacitor value
is easily calculated:
C = VFS 4 • 256 ,
RINT 4V • fCLOCK
where fCLOCK is the crystal or external oscillator frequency
and VFS is the maximum input voltage.
The integration capacitor should be selected for low
dielectric absorption to prevent roll-over errors. A polypro-
pylene, polyester or polycarbonate dielectric capacitor is
recommended.
Reference Capacitors
The reference capacitors require a low leakage dielec-
tric, such as polypropylene, polyester or polycarbonate. A
value of 1µF is recommended for operation over the tem-
perature range. If high-temperature operation is not re-
quired, the CREF values can be reduced.
Auto-Zero Capacitors
Five capacitors are required to auto-zero the input
buffer, integrator amplifier, and comparator. Recommended
capacitors are 0.1µF film dielectric (such as polyester or
polypropylene). Ceramic capacitors are not recommended.
DIGITAL SECTION APPLICATION
Oscillator
The TC850 may operate with a crystal oscillator. The
crystal selected should be designed for a Pierce oscillator,
such as an AT-cut quartz crystal. The crystal oscillator
schematic is shown in Figure 6.
Since low frequency crystals are very large and ceramic
resonators are too lossy, the TC850 clock should be derived
from an external source, such as a microprocessor clock.
The clock should be input on the OSC1 pin and no connec-
tion should be made to the OSC2 pin. The external clock
should swing between DGND and VDD.
Since oscillator frequency is ÷ 4 internally and each
conversion requires 1280 internal clock cycles, the conver-
sion time will be:
Conversion time = fCLOCK × 4 × 1280.
An important advantage of the integrating ADC is the
ability to reject periodic noise. This feature is most often
used to reject line frequency (50Hz or 60Hz) noise. Noise
rejection is accomplished by selecting the integration period
equal to one or more line frequency cycles. The desired
clock frequency is selected as follows:
TELCOM SEMICONDUCTOR, INC.
fCLOCK = fNOISE × 4 × 256,
where fNOISE is the noise frequency to be rejected, 4 repre-
sents the clock divider, and 256 is the number of integrate
cycles.
For example, 60Hz noise will be rejected with a clock
frequency of 61.44kHz, giving a conversion rate of 12
conversions/sec. Integer submultiples of 61.44kHz (such as
30.72kHz, etc.) will also reject 60Hz noise. For 50Hz noise
rejection, a 51.2kHz frequency is recommended.
If noise rejection is not important, other clock frequen-
cies can be used. The TC850 will typically operate at
conversion rates ranging from 3 to 40 conversions/sec,
corresponding to oscillator frequencies from 15.36kHz to
204.8kHz.
2
3
TC850
10 M
4÷4
SYSTEM
CLOCK
17 61.44 kHz
18
100 pF
100 pF
5
Figure 6. Crystal Oscillator Schematic
Data Bus Interfacing
The TC850 provides an easy and flexible digital inter-
face. A 3-state data bus and six control inputs permit the
TC850 to be treated as a memory device, in most applica-
tions. The conversion result can be accessed over an 8-bit
bus or via a µP I/O port.
A typical µP bus interface for the TC850 is shown in
Figure 7. In this example, the TC850 operates in the demand
mode, and conversion begins when a write operation is
performed to any decoded address space. The BUSY
output interrupts the µP at the end-of-conversion.
The A/D conversion result is read as three memory
bytes. The two LSBs of the address bus select high/low byte
and overrange/polarity bit data, while high-order address
lines enable the CE input.
Figure 8 shows a typical interface to a µP I/O port or
single-chip µC. The TC850 operates in the continuous
mode, and can either interrupt the µC/µP or be polled with an
input pin.
6
7
8
3-87

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