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PDF TC74VHCT574AF Data sheet ( Hoja de datos )

Número de pieza TC74VHCT574AF
Descripción OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
Fabricantes Toshiba 
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TC74VHCT574AF/AFW/AFT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT574AF,TC74VHCT574AFW,TC74VHCT574AFT
Octal D-Type Flip-Flop with 3-State Output
The TC74VHCT574A is an advanced high speed CMOS OCTAL
FLIP-FLOP with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type flip-flop is controlled by a clock input (CK)
and a output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output (Note) pins without regard to
the supply voltage. These structure prevents device destruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note: Output in off-state
Features
High speed: fmax = 140 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
Power down protection is provided on all inputs and outputs.
Balanced propagation delays: tpLH ∼− tpHL
Low noise: VOLP = 1.6 V (max)
Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 574 type.
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHCT574AF
TC74VHCT574AFW
TC74VHCT574AFT
Weight
SOP20-P-300-1.27A
SOP20-P-300-1.27
SOL20-P-300-1.27
TSSOP20-P-0044-0.65A
: 0.22 g (typ.)
: 0.22 g (typ.)
: 0.46 g (typ.)
: 0.08 g (typ.)
1 2006-06-01

1 page




TC74VHCT574AF pdf
TC74VHCT574AF/AFW/AFT
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(CK-Q)
3-state output enable
time
3-state output disable
time
Maximum clock
frequency
Output to output skew
Input capacitance
Output capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
fmax
tosLH
tosHL
CIN
COUT
CPD
Test Condition
VCC (V) CL (pF)
15
5.0 ± 0.5
50
RL = 1 k
5.0 ± 0.5
15
50
Ta = 25°C
Min Typ. Max
4.1 9.4
5.6 10.4
6.5 10.2
7.3 11.2
RL = 1 k
5.0 ± 0.5
5.0 ± 0.5
50
15
50
7.0 11.2
90 140
85 130
(Note 1) 5.0 ± 0.5
50
― ― 1.0
― ― 4 10
― ―9
(Note 2) 25
Ta =
40 to 85°C
Min Max
1.0 10.5
1.0 11.5
1.0 11.5
1.0 12.5
Unit
ns
ns
1.0 12.0 ns
80
MHz
75
1.0 ns
10 pF
― ― pF
― ― pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm tpLHn|, tosHL = |tpHLm tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per F/F)
And the total CPD when n pcs. of latch operate can be gained by the following equation:
CPD (total) = 14 + 11·n
Noise Characteristics (input: tr = tf = 3 ns) (Note)
Characteristics
Symbol
Test Condition
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
Minimum high level dynamic input voltage
Maximum low level dynamic input voltage
VIHD
VILD
CL = 50 pF
CL = 50 pF
Note: The value in ( ) only applies to JEDEC SOP (FW) devices.
VCC (V)
5.0
5.0
5.0
5.0
Ta = 25°C
Typ. Max
1.1 1.5
(1.2) (1.6)
1.1 1.5
(1.2) (1.6)
2.0
0.8
Unit
V
V
V
V
5 2006-06-01

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