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PDF TC74VHCT373AFT Data sheet ( Hoja de datos )
| Número de pieza | TC74VHCT373AFT | |
| Descripción | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | |
| Fabricantes | Toshiba | |
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TC74VHCT373AF/AFW/AFT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT373AF,TC74VHCT373AFW,TC74VHCT373AFT
Octal D-Type Latch with 3-State Output
The TC74VHCT373A is an advanced high speed CMOS OCTAL
LATCH with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type latch is controlled by a latch enable input
(LE) and a output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output (Note) pins without regard to
the supply voltage. These structure prevents device destruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note: Output in off-state
Features
• High speed: tpd = 7.7 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
• Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
• Power down protection is provided on all inputs and outputs.
• Balanced propagation delays: tpLH ∼− tpHL
• Low noise: VOLP = 1.6 V (max)
• Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 373 type.
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHCT373AF
TC74VHCT373AFW
TC74VHCT373AFT
Weight
SOP20-P-300-1.27A
SOP20-P-300-1.27
SOL20-P-300-1.27
TSSOP20-P-0044-0.65A
: 0.22 g (typ.)
: 0.22 g (typ.)
: 0.46 g (typ.)
: 0.08 g (typ.)
1 2006-06-01
1 page  
TC74VHCT373AF/AFW/AFT
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(LE-Q)
Propagation delay
time
(D-Q)
3-state output enable
time
3-state output disable
time
Output to output skew
Input capacitance
Output capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
tosLH
tosHL
CIN
COUT
CPD
Test Condition
VCC (V) CL (pF)
15
― 5.0 ± 0.5
50
―
RL = 1 kΩ
5.0 ± 0.5
5.0 ± 0.5
15
50
15
50
Ta = 25°C
Min Typ. Max
― 7.7 12.3
― 8.5 13.3
― 5.1 8.5
― 5.9 9.5
― 6.3 10.9
― 7.1 11.9
RL = 1 kΩ
5.0 ± 0.5
50
― 8.8 11.2
(Note 1) 5.0 ± 0.5
50
― ― 1.0
― ― 4 10
― ―9―
(Note 2) ― 25 ―
Ta =
−40 to 85°C
Min Max
1.0 13.5
1.0 14.5
1.0 9.5
1.0 10.5
1.0 12.5
1.0 13.5
1.0 12.0
― 1.0
― 10
――
――
Unit
ns
ns
ns
ns
ns
pF
pF
pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per latch)
And the total CPD when n pcs. of latch operate can be gained by the following equation:
CPD (total) = 14 + 11·n
Noise Characteristics (input: tr = tf = 3 ns) (Note)
Characteristics
Symbol
Test Condition
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
Minimum high level dynamic input voltage
Maximum low level dynamic input voltage
VIHD
VILD
CL = 50 pF
CL = 50 pF
Note: The value in ( ) only applies to JEDEC SOP (FW) devices.
VCC (V)
5.0
5.0
5.0
5.0
Ta = 25°C
Typ. Max
1.1 1.5
(1.2) (1.6)
−1.1 −1.5
(−1.2) (−1.6)
― 2.0
― 0.8
Unit
V
V
V
V
5 2006-06-01
5 Page | ||
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| PDF Descargar | [ Datasheet TC74VHCT373AFT.PDF ] | |
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