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PDF TC74VHC574 Data sheet ( Hoja de datos )
| Número de pieza | TC74VHC574 | |
| Descripción | OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TC74VHC574F/FW/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC574F,TC74VHC574FW,TC74VHC574FT,TC74VHC574FK
Octal D-Type Flip Flop with 3-State Output
The TC74VHC574 is advanced high speed CMOS OCTAL
FLIP-FLOP with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type flip-flop is controlled by a clock input (CK)
and a output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
• High speed: fmax = 180 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Low noise: VOLP = 1.2 V (max)
• Pin and function compatible with 74ALS574
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHC574F
TC74VHC574FW
TC74VHC574FT
TC74VHC574FK
Weight
SOP20-P-300-1.27A
: 0.22 g (typ.)
SOP20-P-300-1.27
: 0.22 g (typ.)
SOL20-P-300-1.27
: 0.46 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
VSSOP20-P-0030-0.50 : 0.03 g (typ.)
1 2006-02-01
1 page  
TC74VHC574F/FW/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(CK-Q)
3-state output enable
time
3-state output disable
time
Maximum clock
frequency
Output to output skew
Input capacitance
Output capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
fmax
tosLH
tosHL
CIN
COUT
CPD
Test Condition
VCC (V)
3.3 ± 0.3
―
5.0 ± 0.5
RL = 1 kΩ
3.3 ± 0.3
5.0 ± 0.5
RL = 1 kΩ
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
―
5.0 ± 0.5
3.3 ± 0.3
(Note 1)
5.0 ± 0.5
―
―
CL (pF)
15
50
15
50
15
50
15
50
50
50
15
50
15
50
50
50
Ta = 25°C
Min Typ. Max
― 8.5 13.2
― 11.0 16.7
― 5.6 8.6
― 7.1 10.6
― 8.2 12.8
― 10.7 16.3
― 5.9 9.0
― 7.4 11.0
― 11.0 15.0
― 7.1 10.1
80 125 ―
50 75 ―
130 180
―
85 115 ―
― ― 1.5
― ― 1.0
― 4 10
―6―
(Note 2) ― 28 ―
Ta =
−40 to 85°C
Min Max
1.0 15.5
1.0 19.0
1.0 10.0
1.0 12.0
1.0 15.0
1.0 18.5
1.0 10.5
1.0 12.5
1.0 17.0
1.0 11.5
65 ―
45 ―
110 ―
75 ―
― 1.5
― 1.0
― 10
――
――
Unit
ns
ns
ns
MHz
ns
pF
pF
pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per F/F)
And the total CPD when n pcs. of latch operate can be gained by the following equation:
CPD (total) = 20 + 8·n
5 2006-02-01
5 Page 
Package Dimensions
TC74VHC574F/FW/FT/FK
Weight: 0.03 g (typ.)
11 2006-02-01
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet TC74VHC574.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TC74VHC573F | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
| TC74VHC573FK | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
| TC74VHC573FT | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
| TC74VHC573FW | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
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