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PDF TC74VHC257FN Data sheet ( Hoja de datos )

Número de pieza TC74VHC257FN
Descripción QUAD 2-CHANNEL MULTIPLEXER (3-STATE)
Fabricantes Toshiba 
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TC74VHC257F/FN/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC257F,TC74VHC257FN,TC74VHC257FT,TC74VHC257FK
Quad 2-Channel Multiplexer (3-state)
The TC74VHC257 is an advanced high speed CMOS
MULTIPLEXER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
It is composed of four independent 2-channel multiplexers with
common SELECT and OUTPUT ENABLE ( OE ).
If OE is set low, the outputs are held in a high-impedance
state. When SELECT is set low, “A” data inputs are enabled.
Conversely, when SELECT is high, “B” data inputs are
enabled.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
High speed: tpd = 3.6 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
Low noise: VOLP = 0.8 V (max)
Pin and function compatible with 74ALS257
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74VHC257F
TC74VHC257FN
TC74VHC257FT
TC74VHC257FK
Weight
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
VSSOP16-P-0030-0.50
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1 2007-10-01

1 page




TC74VHC257FN pdf
TC74VHC257F/FN/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(A, B-Y)
Propagation delay
time
(SELECT-Y)
3-state output enable
time
3-state output disable
time
Input capacitance
Onput capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
CIN
COUT
CPD
Test Condition
RL = 1 k
RL = 1 k
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
CL (pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
Ta = 25°C
Min Typ. Max
5.8 9.3
8.3 12.8
3.6 5.9
5.1 7.9
7.0 11.0
9.5 14.5
4.0 6.8
5.5 8.8
6.7 10.5
9.2 14.0
3.6 6.8
5.1 8.8
8.6 12.0
5.7 7.9
4 10
6
(Note) 23
Ta = 40 to
85°C
Min Max
1.0 11.0
1.0 14.5
1.0 7.0
1.0 9.0
1.0 13.0
1.0 16.5
1.0 8.0
1.0 10.0
1.0 12.5
1.0 16.0
1.0 8.0
1.0 10.0
1.0 13.5
1.0 9.0
10
――
――
Unit
ns
ns
ns
ns
pF
pF
pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/4 (per bit)
Noise Characteristics (input: tr = tf = 3 ns)
Characteristics
Symbol
Test Condition
Quiet output maximum dynamic VOL
Quiet output minimum dynamic VOL
Minimum high level dynamic input voltage
Maximum low level dynamic input voltage
VOLP
VOLV
VIHD
VILD
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
VCC (V)
5.0
5.0
5.0
5.0
Ta = 25°C
Typ. Max
0.3 0.8
0.3 0.8
3.5
1.5
Unit
V
V
V
V
Input Equivalent Circuit
INPUT
5 2007-10-01

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