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PDF TC74VHC240FW Data sheet ( Hoja de datos )

Número de pieza TC74VHC240FW
Descripción OCTAL BUS BUFFER
Fabricantes Toshiba 
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No Preview Available ! TC74VHC240FW Hoja de datos, Descripción, Manual

TC74VHC240,244F/FW/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC240F,TC74VHC240FW,TC74VHC240FT,TC74VHC240FK
TC74VHC244F,TC74VHC244FW,TC74VHC244FT,TC74VHC244FK
Octal Bus Buffer
TC74VHC240F/FW/FT/FK
Inverted, 3-State Outputs
TC74VHC244F/FW/FT/FK
Non-Inverted, 3-State Outputs
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHC240F, TC74VHC244F
The TC74VHC240 and 244 are advanced high speed CMOS
OCTAL BUS BUFFERs fabricated with silicon gate C2MOS
technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The 74VHC240 is an inverting 3-state buffer having two
active-low output enables. The TC74VHC244 is a non-inverting
3-state buffer, and has two active-low output enables.
These devices are designed to be used with 3-state memory
address drivers, etc.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
High speed: tpd = 3.9 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
Low noise: VOLP = 0.9 V (max)
Pin and function compatible with 74ALS240/244
TC74VHC240FW, TC74VHC244FW
TC74VHC240FT, TC74VHC244FT
TC74VHC240FK, TC74VHC244FK
Weight
SOP20-P-300-1.27A
: 0.22 g (typ.)
SOP20-P-300-1.27
: 0.22 g (typ.)
SOL20-P-300-1.27
: 0.46 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
VSSOP20-P-0030-0.50 : 0.03 g (typ.)
1 2006-02-01

1 page




TC74VHC240FW pdf
TC74VHC240,244F/FW/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(TC74VHC240)
Propagation delay
time
(TC74VHC244)
3-state output enable
time
3-state output disable
time
Output to output skew
Input capacitance
Output capacitance
Power dissipation
capacitance (Note 2)
Symbol
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
tosLH
tosHL
CIN
COUT
CPD
Test Condition
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
RL = 1 k
3.3 ± 0.3
5.0 ± 0.5
RL = 1 k
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
(Note 1)
5.0 ± 0.5
TC74VHC240
TC74VHC244
CL (pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
50
50
Ta = 25°C
Min Typ. Max
5.3 7.5
7.8 11.0
3.6 5.5
5.1 7.5
5.8 8.4
8.3 11.9
3.9 5.5
5.4 7.5
6.6 10.6
9.1 14.1
4.7 7.3
6.2 9.3
10.3 14.0
6.7 9.2
⎯ ⎯ 1.5
⎯ ⎯ 1.0
4 10
6
17
19
Ta =
40 to 85°C
Min Max
1.0 9.0
1.0 12.5
1.0 6.5
1.0 8.5
1.0 10.0
1.0 13.5
1.0 6.5
1.0 8.5
1.0 12.5
1.0 16.0
1.0 8.5
1.0 10.5
1.0 16.0
1.0 10.5
1.5
1.0
10
⎯⎯
⎯⎯
⎯⎯
Unit
ns
ns
ns
ns
ns
pF
pF
pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm tpLHn|, tosHL = |tpHLm tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per bit)
Noise Characteristics (input: tr = tf = 3 ns) (Note)
Characteristics
Symbol
Test Condition
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
Minimum high level dynamic input
voltage
Maximum low level dynamic input
voltage
VIHD
VILD
CL = 50 pF
CL = 50 pF
Note: The value in ( ) only applies to JEDEC SOP (FW) devices.
VCC (V)
5.0
5.0
Ta = 25°C
Typ. Limit
0.5 0.8
(0.6) (0.9)
0.5 0.8
(0.6) (0.9)
Unit
V
V
5.0
3.5
V
5.0
1.5
V
5 2006-02-01

5 Page





TC74VHC240FW arduino
Package Dimensions
TC74VHC240,244F/FW/FT/FK
Weight: 0.03 g (typ.)
11 2006-02-01

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