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PDF PCM78P Data sheet ( Hoja de datos )
| Número de pieza | PCM78P | |
| Descripción | 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® PCM78P
16-Bit Audio
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q LOW COST/HIGH PERFORMANCE 16-BIT
AUDIO A/D CONVERTER
q FAST 5µs MAX CONVERSION TIME
(4µs typ)
q VERY LOW THD+N ( typ –88dB at FS;
max –82dB)
q ±3V INPUT RANGE
q TWO SERIAL OUTPUT MODES PROVIDE
VERSATILE INTERFACING
q COMPLETE WITH INTERNAL REFERENCE
AND CLOCK IN 28-PIN PLASTIC DIP
q ±5V TO ±15V SUPPLY RANGE (600mW
Power Dissipation)
APPLICATIONS
q DSP DATA ACQUISITION
q TEST INSTRUMENTATION
q SAMPLING KEYBOARD SYNTHESIZERS
q DIGITAL AUDIO TAPE
q BROADCAST AUDIO PROCESSING
q TELECOMMUNICATIONS
DESCRIPTION
The PCM78P is a low-cost 16-bit analog-to-digital
converter which is specifically designed and tested for
dynamic applications. It features very fast, low
distortion performance (4µs/–88dB THD+N typical)
and is complete with internal clock and reference
circuitry. The PCM78P is packaged in a reliable, low-
cost 28-pin plastic DIP and data output is available in
user-selectable serial output formats. The PCM78P is
ideal for digital audio tape (DAT) recorders. Many
similar applications such as digital signal processing
and telecom applications are equally well served by
the PCM78P.
The PCM78P uses a SAR technique. Analog and
digital portions are efficiently partitioned into a high-
speed, bipolar section and a low-power CMOS
section. The PCM78P has been optimized for excel-
lent dynamic performance and low cost.
Audio Input
16-bit D/A
Converter
–
Comp
+
Convert
Command
16-bit SAR +
Timing Control
Internal
Clock
Circuit
External Clock
Status
Serial Output 1
Serial Output 2
Clock Output
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1989 Burr-Brown Corporation
PDS-989A
Printed in U.S.A. October, 1993
1 page  
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = ±15V, unless otherwise noted.
7.00
INTEGRAL NONLINEARITY
at –25°C
6.00
5.00
4.00
3.00
2.00
1.00
0.00
–1.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Major Carry Bit Number
1.40
1.20
DIFFERENTIAL NONLINEARITY
at –25°C
1.00
0.80
0.60
0.40
0.20
0.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Major Carry Bit Number
INTEGRAL NONLINEARITY
at 0°C
5.00
4.00
3.00
2.00
1.00
0.00
–1.00
–2.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Major Carry Bit Number
1.40
1.20
DIFFERENTIAL NONLINEARITY
at 0°C
1.00
0.80
0.60
0.40
0.20
0.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Major Carry Bit Number
5.00
4.00
INTEGRAL NONLINEARITY
at 25°C
3.00
2.00
1.00
0.00
–1.00
–2.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Major Carry Bit Number
1.40
1.20
DIFFERENTIAL NONLINEARITY
at 25°C
1.00
0.80
0.60
0.40
0.20
0.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Major Carry Bit Number
®
5 PCM78
5 Page 
In either case, the PCM78 requires 17 clock cycles to
complete a conversion. To calculate the clock frequency
necessary for a given conversion time, the following equa-
tion may be used:
f
CLOCK
=
17
Conversion
Time
The internal clock operates only during a conversion, and is
gated on by the falling edge of the convert command. See
Figure 6. The internal clock is available on pin 10, Clock
Out. The high and low time of this clock is set by R1C1 and
R2C2 respectively. The duty cycle of the clock should be
between 20% to 80%, and may be set to 50% for simplicity.
Clock High Time (in ns) = 1.32R1C1
Clock Low Time (in ns) = 1.32R2C2
R in kΩ; C in pF.
These equations are approximate (±5%); they should be
used for determining an initial part value which will then
need to be “tweaked” for accurate timing. If highly accurate
time bases are required, use of an external clock is recom-
mended.
The external clock is applied at pin 16, and the Int/Ext
Clock select (pin 17) should be left open (an internal pull-
up resistor assures that the logical state of an open pin is
“1”). Using the external clock requires careful placement in
time of the convert command. Figure 7 diagrams the recom-
mended timing with an external clock. A simple circuit
which assures the proper timing of the convert command is
shown in Figure 8.
Due to the design of the Clock/Logic chip in the PCM78, a
conversion is begun inside the PCM78 by an asynchronous
state machine. This places stringent requirements on the
timing of the convert command, as improper timing can
cause metastable states within this state machine. Using the
circuitry shown in Figure 8, the user is assured of consistent
operation, and these invalid states within the state machine
are entirely avoided. (Note that this is not a consideration
when using an internal clock, as nothing is being clocked
when a convert command is presented to the PCM78).
The Clock Out function is a gated form of the external
clock, i.e. the 17 clock cycles used in the conversion are
present on this pin during conversion. This allows use of a
continuous external clock, with Clock Out being the clock
that the converter is actually using for conversion. Note that
this is simply a delayed (~24ns) version of the external
clock, and will have the same frequency and duty cycle.
The SOUT2 Latch enables the user to latch data from the
previous conversion and read it out at a higher speed than
the convert clock. This feature allows the converter to
easily interface to digital filtering necessary for
oversampling. See Figure 9 for timing information in this
mode.
In this mode, the PCM78 generates its own internal convert
command when the SOUT2 Clock goes high within ±50ns of
SOUT2 Latch going low; the external convert command may
not be used, and pin 19 must be grounded. The timing
diagram shows the recommended timing for using this
mode. After the SOUT2 Latch control signal goes low, data
from the SAR is loaded into the SOUT2 latch on the next
rising edge of the SOUT2 Clock. This clock edge should
occur prior to the next rising edge of the conversion clock
(internal or external), since the SAR will reset itself prior to
the latching
Convert
Command
Clock Out
T1
T2
T3
T4
T5
T7
Status
SOUT 1
Data
T6
PCM78 TIMING SPECIFICATIONS
TA = +25°C, VDD = +5V, guaranteed by sample testing; these parameters are not 100% tested in production.
TIME DESCRIPTION
TIME (ns)
MIN TYP MAX
T1 CONVERT COMMAND pulse width
T2 Delay from falling edge of CONVERT COMMAND to rising edge of CLOCK OUT
T3 Delay from rising edge of CLOCK OUT to rising edge of STATUS
T4 INTERNAL CLOCK pulse width
T5 INTERNAL CLOCK period
T6 Delay from rising edge of CLOCK OUT to bit data valid
T7 Delay from rising edge of 17th clock pulse to falling edge of STATUS
25 50
(1)
60 70 85
8 10 30
50 125 450
140 290 500
17 20 50
10 15 30
NOTE: (1) When using the internal clock, the clock does not operate until the Convert Command is low. It is therefore possible to keep the convert command
high indefinitely, thereby keeping the PCM78 in a halt mode. The conversion cycle begins on the falling edge of convert command, and convert command must
remain low during the entire conversion cycle in order to make the PCM78 operate properly.
FIGURE 6. Conversion Timing when using Internal Clock.
11 PCM78
®
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet PCM78P.PDF ] | |
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