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PDF IDT74ALVC16245 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVC16245 | |
| Descripción | 3.3V CMOS 16-BIT BUS TRANSCEIVER | |
| Fabricantes | Integrated Device Tech | |
| Logotipo |  |
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IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
3.3V CMOS 16-BIT
BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
IDT74ALVC16245
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
DESCRIPTION:
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. The ALVC16245 is designed for asynchronous communication
between data buses. The control-function implementation minimizes external
timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
It allows data transmission from the A bus to the B bus or from the B bus to the
A bus, depending on the logic level at the direction-control (DIR) input. The
output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.
The ALVC16245 has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1DIR 1
1A1 47
1A2 46
1A3 44
1A4 43
1A5 41
1A6 40
1A7 38
1A8 37
48 1OE
2 1B1
3 1B2
5 1B3
6 1B4
8 1B5
9 1B6
11 1B7
12 1B8
2DIR 24
2A1 36
2A2 35
2A3 33
2A4 32
2A5 30
2A6 29
2A7 27
2A8 26
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2009 Integrated Device Technology, Inc.
1
25 2OE
13 2B1
14 2B2
16 2B3
17 2B4
19 2B5
20 2B6
22 2B7
23 2B8
JUNE 2009
DSC-4604/6
1 page  
IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
VCC
Pulse(1, 2)
Generator
VIN
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
ALVC Link
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
VIH
VT
0V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VLOAD/2
VT
tPHZ
VT
0V
VLOAD/2
VOL + VLZ
VOL
VOH
VOH - VHZ
0V
ALVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
Set-up, Hold, and Release Times
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
ALVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
VT
VT
ALVC Link
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVC16245.PDF ] | |
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