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PDF IDT73720APQF Data sheet ( Hoja de datos )

Número de pieza IDT73720APQF
Descripción 16-BIT TRI-PORT BUS EXCHANGER
Fabricantes Integrated Device Tech 
Logotipo Integrated Device Tech Logotipo



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16-BIT TRI-PORT
BUS EXCHANGER
IDT73720/A
Integrated Device Technology, Inc.
FEATURES:
• High-speed 16-bit bus exchange for interbus communica-
tion in the following environments:
— Multi-way interleaving memory
— Multiplexed address and data busses
• Direct interface to R3051 family RISChipSet
— R3051family of integrated RISControllerCPUs
— R3721 DRAM controller
• Data path for read and write operations
• Low noise 12mA TTL level outputs
• Bidirectional 3-bus architecture: X, Y, Z
— One CPU bus: X
— Two (interleaved or banked) memory busses:Y & Z
— Each bus can be independently latched
• Byte control on all three busses
• Source terminated outputs for low noise and undershoot
control
• 68-pin PLCC and 80-pin PQFP package
• High-performance CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT73720/A Bus Exchanger is a high speed 16-bit bus
exchange device intended for inter-bus communication in
interleaved memory systems and high performance multi-
plexed address and data busses.
The Bus Exchanger is responsible for interfacing between
the CPU A/D bus (CPU address/data bus) and multiple
memory data busses.
The 73720/A uses a three bus architecture (X, Y, Z), with
control signals suitable for simple transfer between the CPU
bus (X) and either memory bus (Y or Z). The Bus Exchanger
features independent read and write latches for each memory
bus, thus supporting a variety of memory strategies. All three
ports support byte enable to independently enable upper and
lower bytes.
LEXY
LEYX
88
OEXL
OEYL
8
Y-WRITE
LATCH
16
8
Y-READ
LATCH
16
8
OEYU
16
8
Y0:7
Y8:15
(Even Path)
X0:7
X8:15
8
M
U
16 X
8
OEXU
OEXL
OEYU
OEYL
OEZU
OEZL
BUS CONTROL
PATH
T/R
OEU
OEL
LEZX
LEXZ
OEXU
88
16
16
Z-READ
LATCH
16 OEZL
8
8
Z-WRITE
LATCH
16
8
OEZU
NOTE:
Figure 1. 73720 Block Diagram
1. Logic equations for bus control:
OEXU = T/R* . OEU*; OEXL = T/R* . OEL*; OEYU = T/R . PATH . OEU*
OEYL = T/R . PATH . OEL*; OEZU = T/R . PATH* . OEU*; OEZL = T/R . PATH* . OEL*
8
Z0:7
Z8:15
(Odd Path)
2527 drw 01
RISChipSet, RISController, R305x, R3051, R3052 are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 1995
©1995 Integrated Device Technology, Inc.
11.5
DSC-2046/6
1

1 page




IDT73720APQF pdf
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
Clk2xIn
IDT R3051 FAMILY
RISController
ADDRESS/DATA
R305x
LOCAL BUS
IDT79R3721
DRAM
CONTROLLER
COMMERCIAL TEMPERATURE RANGE
CONTROL
DRAM
DRAM
IDT73720
BUS EXCHANGER
(2)
CPU
4 x (74FCT373)
Figure 2. Bus Exchanger Used in R3051 Family System
32
2 x (73720)
CPU
4 x (74FCT373)
2527 drw 04
32
2 x (73720)
Address
DRAM 1 DRAM 2
Data Bus Chip Count = 2 Pin Count = 136
Address
DRAM 1 DRAM 2
Data Bus Chip Count = 2 Pin Count = 136
CPU
CPU
32
32
4 x (74FCT373)
4 x (74FCT245) 4 x (74FCT245)
4 x (74FCT373)
4 x (74FCT543) 4 x (74FCT543)
Address
DRAM 1
DRAM 2
Address
DRAM 1
DRAM 2
Data Bus Chip Count = 8 Pin Count = 160
2527 drw 05
Figure 3. CPU System with Transparent Data Path
(2-way Interleaving)
Data Bus Chip Count = 8 Pin Count = 192
2527 drw 06
Figure 4. CPU System with Latched Data Path
(2-way Interleaving)
11.5 5

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