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PDF IDT72V8980PV Data sheet ( Hoja de datos )
| Número de pieza | IDT72V8980PV | |
| Descripción | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256 | |
| Fabricantes | Integrated Device Tech | |
| Logotipo |  |
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3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT72V8980
FEATURES:
• 256 x 256 channel non-blocking switch
• Serial Telecom Bus Compatible (ST-BUS®)
• 8 RX inputs—32 channels at 64 Kbit/s per serial line
• 8 TX output—32 channels at 64 Kbit/s per serial line
• Three-state serial outputs
• Microprocessor Interface (8-bit data bus)
• 3.3V Power Supply
• Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 48-pin
Small Shrink Outline Package (SSOP), and 44-pin Plastic Quad
Flatpack (PQFP)
• Operating Temperature Range -40°C to +85°C
• 3.3V I/O with 5V Tolerant Inputs
DESCRIPTION:
The IDT72V8980 is a ST-BUS® compatible digital switch controlled by a
microprocessor. TheIDT72V8980canhandleasmanyas256,64Kbit/sinput
and output channels. Those 256 channels are divided into 8 serial inputs and
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form
a multiplexed 2.048 Mb/s stream.
FUNCTIONAL DESCRIPTION
A functional block diagram of the IDT72V8980 device is shown on below.
The serial ST-BUS® streams operate continuously at 2.048 Mb/s and are
arrangedin125µswideframeseachcontaining32,8-bitchannels. Eightinput
(RX0-7) and eight output (TX0-7) serial streams are provided in the
IDT72V8980 device allowing a complete 256 x 256 channel non-blocking
switch matrix to be constructed. The serial interface clock (C4i) for the device
is 4.096 MHz.
The received serial data is internally converted to a parallel format by the
on chip serial-to-parallel converters and stored sequentially in a 256-position
Data Memory. By using an internal counter that is reset by the input 8 KHz frame
pulse, F0i, the incoming serial data streams can be framed and sequentially
addressed.
FUNCTIONAL BLOCK DIAGRAM
C4i F0i VCC GND
RESET(1)
ODE
RX0 Timing
Unit Output MUX
RX1
RX2
Receive
RX3 Serial Data
Data
RX4 Streams Memory
Transmit
Serial Data
Streams
RX5
Control Register
Connection
RX6 Memory
RX7 Microprocessor Interface
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
DS CS R/W A0 DTA D0/
A5/ D5
CCO
5705 drw01
NOTE:
1. The RESET Input is only provided on the SSOP package.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
DSC-5705/5
1 page  
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) the output stream and channel.
The contents of bit 1 (CCO) of each Connection Memory High Location (see
Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s
output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on
CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the
CCOoutputistransmittedinLOW. Thecontentsofthe256CCObitsoftheCMH
are transmitted sequentially on to the CCO output pin and are synchronous to
theTXstreams. Toallowfordelayinanyexternalcontrolcircuitrythecontents
of the CCO bit is output one channel before the corresponding channel on the
TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding
toTX0,CH0)istransmittedsynchronouslywiththeTXchannel31,bit7. Bit1's
of CMH for channel 1 of streams 0-7 are output synchronously with TX channel
0 bits 7-0.
INITIALIZATION OF THE IDT72V8980
On initialization or power up, the contents of the Connection Memory High
canbeinanystate. ThisisapotentiallyhazardousconditionwhenmultipleTX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
intothehighimpedancestate. CareshouldbetakenthatnotwoconnectedTX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
RESET
The reset pin is designed to be used with board reset circuitry. During reset
the TX serial streams will be put into high-impedance and the state of internal
registers and counters will be reset. As the connection memory can be in any
state after a power up, the ODE pin should be used to hold the TX streams in
high-impedance until the per-channel output enable control in the connection
memory high is appropriately programmed. The main difference between ODE
and reset is, reset alters the state of the registers and counters where as ODE
controls only the high-impedance state of the TX streams. RESET input is only
provided on the SSOP package.
TABLE 1 — INPUT STREAM TO OUTPUT
STREAM COMBINATIONS THAT CAN
PROVIDE THE MINIMUM 2-CHANNEL
DELAY
Input
Output Stream
0 1,2,3,4,5,6,7
1 3,4,5,6,7
2 5,6,7
37
4 1,2,3,4,5,6,7
5 3,4,5,6,7
6 5,6,7
77
TABLE 2 — ADDRESS MAPPING
A5 A4 A3 A2 A1 A0 HEX ADDRESS
LOCATION
0XXXXX
100000
100001
00-1F
20
21
Control Register(1)
Channel 0(2)
Channel 1(2)
••••••
•
•
••••••
•
•
••••••
111111
•
3F
•
Channel 31(2)
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
Control Register CRb7 CRb6 CRb5 CRb4 CRb3 CRb2 CRb1 CRb0
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CRb4
0
1
1
CRb3
1
0
1
Connection Memory High
Connection Memory Low
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Data Memory
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
CRb2
0
0
0
0
1
1
1
1
CRb1
0
0
1
1
0
0
1
1
CRb0 Stream
00
11
02
13
04
15
06
17
100000
100001
100010
111111
External Address Bits A5-A0
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Figure 3. Address Mapping
5
5 Page 
ORDERING INFORMATION
IDT XXXXXX
Device Type
XX
Package
X
Process/
Temperature
Range
BLANK Commercial (-40°C to +85°C)
J Plastic Leaded Chip Carrier (PLCC, J44-1)
PV Small Shrink Outline Package (SSOP,SO48-1)
DB Plastic Quad Flatpack (PQFP, DB44-1)
72V8980 256 x 256 3.3V Time Slot Interchange Digital Switch
5705 drw16
DATASHEET DOCUMENT HISTORY
05/23/2000 pgs. 1, 2, and 11.
08/18/2000 pgs. 1, 2 and 11.
01/24/2001 pgs. 1 and 7.
03/10/2003 pg. 1.
05/09/2003 pgs. 1, 2 and 11.
08/20/2003 pg. 7.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
11
for Tech Support:
408-330-1753
email: [email protected]
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet IDT72V8980PV.PDF ] | |
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