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PDF IDT72V851 Data sheet ( Hoja de datos )

Número de pieza IDT72V851
Descripción 3.3 VOLT DUAL CMOS SyncFIFO
Fabricantes Integrated Device Tech 
Logotipo Integrated Device Tech Logotipo



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No Preview Available ! IDT72V851 Hoja de datos, Descripción, Manual

3.3 VOLT DUAL CMOS SyncFIFO™
DUAL 256 X 9, DUAL 512 X 9,
DUAL 1,024 X 9, DUAL 2,048 X 9,
DUAL 4,096 X 9 , DUAL 8,192 X 9
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
.EATURES:
The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs
The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs
The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs
The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs
The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs
The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time
5V input tolerant
Separate control lines and data lines for each FIFO
Separate Empty, Full, programmable Almost-Empty and
Almost-Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/
STQFP)
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are
dual synchronous (clocked) FIFOs. The device is functionally equivalent to
two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,
QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).
Data is written into each of the two arrays on every rising clock edge of the Write
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are
asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2). The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
FFB). Twoprogrammableflags,Almost-Empty(PAEA, PAEB)andAlmost-Full
(PAFA, PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.
If not programmed, the programmable flags default to Empty+7 for PAEAand
PAEB, and Full-7 for PAFA and PAFB.
The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture
lends itself to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectionaloperation
• Widthexpansion
• Depth expansion
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
.UNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
DA0 - DA8
INPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
OUTPUT REGISTER
EFA WCLKB
PAEA
WENB1
LDA PAFA
FFA
WENB2
OFFSET REGISTER
FLAG
LOGIC
WRITE CONTROL
LOGIC
READ POINTER
READ CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
DB0 - DB8
INPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
OUTPUT REGISTER
LDB
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
EFB
PAEB
PAFB
FFB
READ CONTROL
LOGIC
RSA OEA
RCLKA
QA0 - QA8
RENA1
RENA2
RSB OEB
QB0 - QB8
The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2001 Integrated Device Technology, Inc.
RCLKB
4093 drw 01
RENB1
RENB2
APRIL 2001
DSC-4093/1

1 page




IDT72V851 pdf
IDT72V801/72V811/72V821/72V831/72V841/72V851
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l
IDT72V801L10
IDT72V811L10
IDT72V821L10
IDT72V831L10
IDT72V841L10
IDT72V851L10
Symbol
Parameter
Min. Max.
fS Clock Cycle Frequency
— 100
tA Data Access Time
2 6.5
tCLK Clock Cycle Time
10 —
tCLKH
Clock High Time
4.5 —
tCLKL
Clock Low Time
4.5 —
tDS DataSet-upTime
3—
tDH Data Hold Time
0.5 —
tENS Enable Set-up Time
3—
tENH Enable Hold Time
0.5 —
tRS Reset Pulse Width(2)
10 —
tRSS Reset Set-up Time
8—
tRSR Reset Recovery Time
8—
tRSF Reset to Flag Time and Output Time
— 10
tOLZ Output Enable to Output in Low-Z(3)
0—
tOE Output Enable to Output Valid
36
tOHZ Output Enable to Output in High-Z(3)
36
tWFF Write Clock to Full Flag
— 6.5
tREF Read Clock to Empty Flag
— 6.5
tPAF Write Clock to Programmable Almost-Full Flag
— 6.5
tPAE Read Clock to Programmable Almost-Empty Flag
— 6.5
tSKEW1
Skew Time Between Read Clock and Write Clock
for Empty Flag and Full Flag
5—
tSKEW2
Skew Time Between Read Clock and Write Clock for
Programmable Almost-Empty Flag and Programmable
Almost-Full Flag
14 —
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
IDT72V801L15
IDT72V811L15
IDT72V821L15
IDT72V831L15
IDT72V841L15
IDT72V851L15
Min. Max.
— 66.7
2 10
15(1)
6—
6—
4—
1—
4—
1—
15 —
10 —
10 —
— 15
0—
38
38
— 10
— 10
— 10
— 10
6—
18 —
Commercial
IDT72V801L20
IDT72V811L20
IDT72V821L20
IDT72V831L20
IDT72V841L20
IDT72V851L20
Min. Max.
— 50
2 12
20 —
8—
8—
5—
1—
5—
1—
20 —
12 —
12 —
— 20
0—
3 10
3 10
— 12
— 12
— 12
— 12
8—
20 —
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
5
D.U.T.
510
3.3V
330
30pF*
4093 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.

5 Page





IDT72V851 arduino
IDT72V801/72V811/72V821/72V831/72V841/72V851
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
WCLKA
(WCLKB)
DA0 - DA8
(DB0 - DB8)
FFA (FFB)
WENA1
(WENB1)
WENA2
(WENB2)
(If Applicable)
NO WRITE
tSKEW1
tDS
tWFF
tENS
tENS
tDH
tWFF
tENH
tENH
NO WRITE
tSKEW1
NO WRITE
tWFF
tENS(1)
tENS(1)
RCLKA
(RCLKB)
RENA1
(RENB2)
OEA LOW
(OEB)
tENS
tENH
tA
tENS
QA0 - QA8
(QB0 - QB8)
DATA IN OUTPUT REGISTER
DATA READ
NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
tENH
tA
NEXT DATA READ
4093 drw 10
Figure 8. Full Flag Timing
WCLKA (WCLKB)
DA0 - DA8
(DB0 - DB8)
tDS
tENS
DATA WRITE 1
tENH
WENA1, (WENB1)
tENS
WENA2 (WENB2)
(If Applicable)
RCLKA (RLCKB)
tENH
tSKEW1
(1)
tFRL
EFA (EFB)
tREF
tDS
tENS
DATA WRITE 2
tENH
tENS
tENH
tREF
tSKEW1
(1)
tFRL
tREF
RENA1, RENA2
(RENB1, RENB2)
OEA (OEB)
LOW
QA0 - QA8
(QB0 - QB8)
DATA IN OUTPUT REGISTER
tA
NOTE:
1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 9. Empty Flag Timing
11
DATA READ
4093 drw 11

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