PDF IDT72V845 Data sheet ( Hoja de datos )

Número de pieza	IDT72V845
Descripción	3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18/ DUAL 512 x 18/ DUAL 1/024 x 18/ DUAL 2/048 x 18
Fabricantes	Integrated Device Tech
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No Preview Available ! 3.3 VOLT CMOS DUAL SyncFIFO™ DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 IDT72V805 IDT72V815 IDT72V825 IDT72V835 IDT72V845 FEATURES: • The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs • The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs • The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs • The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs • The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs • Offers optimal combination of large capacity (8K), high speed, design flexibility, and small footprint • Ideal for the following applications: – Network switching – Two level prioritization of parallel data – Bidirectional data transfer – Bus-matching between 18-bit and 36-bit data paths – Width expansion to 36-bit per package – Depth expansion to 8,192 words per package • 10 ns read/write cycle time • 5V input tolerant • IDT Standard or First Word Fall Through timing • Single or double register-buffered Empty and Full Flags • Easily expandable in depth and width • Asynchronous or coincident Read and Write Clocks • Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings • Half-Full flag capability • Output enable puts output data bus in high-impedance state • High-performance submicron CMOS technology • Available in a 128-pin thin quad flatpack (TQFP) • Industrial temperature range (–40°C to +85°C) is available DESCRIPTION: The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide synchronous (clocked) First-in, First-out (FIFO) memories designed to run off a 3.3V supply for exceptionally low power consumption. One dual IDT72V805/72V815/72V825/72V835/72V845 device is functionally equiva- lent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FUNCTIONAL BLOCK DIAGRAM WCLKA WENA DA0-DA17 FFA/IRA HFA/(WXOA) PAEA EFA/ ORA WCLKB LDA PAFA WENB DB0-DB17 LDB INPUT REGISTER OFFSET REGISTER WRITE CONTROL LOGIC FLA WXIA (HFA)/WXOA RXIA RXOA WRITE POINTER EXPANSION LOGIC RSA RESET LOGIC RAM ARRAY 256 x 18 512 x 18 1,024 x 18 2,048 x 18 4,096 x 18 OUTPUT REGISTER FLAG LOGIC READ POINTER READ CONTROL LOGIC INPUT REGISTER WRITE CONTROL LOGIC WRITE POINTER RAM ARRAY 256 x 18 512 x 18 1,024 x 18 2,048 x 18 4,096 x 18 EXPANSION LOGIC RESET LOGIC OUTPUT REGISTER OFFSET REGISTER FLAG LOGIC FFB/IRB PAFB EFB/ORB PAEB HFB/(WXOB) READ POINTER READ CONTROL LOGIC OEA QA0-QA17 RCLKA RENA RSB RXOB RXIB (HFB)/WXOB WXIB FLB OEB QB0-QB17 The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 ©2001 Integrated Device Technology, Inc. RCLKB RENB 4295 drw 01 APRIL 2001 DSC-4295/1 1 page IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C) Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAFA tPAFS tPAEA tPAES tHF tXO tXI tXIS tSKEW1 tSKEW2(4) Parameter Clock Cycle Frequency— Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width(1) Reset Setup Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z(3) Output Enable to Output Valid Output Enable to Output in High-Z(3) Write Clock to Full Flag Read Clock to Empty Flag Clock to Asynchronous Programmable Almost-Full Flag Write Clock to Synchronous Programmable Almost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag Read Clock to Synchronous Programmable Almost-Empty Flag Clock to Half-Full Flag Clock to Expansion Out Expansion In Pulse Width Expansion In Setup Time Skew time between Read Clock & Write Clock for FF/IR and EF/OR Skew time between Read Clock & Write Clock for PAE and PAF Commercial IDT72V805L10 IDT72V815L10 IDT72V825L10 IDT72V835L10 IDT72V845L10 Min. Max. 100 — 2 6.5 10 — 4.5 — 4.5 — 3— 0.5 — 3— 0.5 — 10 — 8— 8— — 15 0— —6 16 — 6.5 — 6.5 — 17 —8 — 17 —8 — 17 — 6.5 3— 3— 5— 14 — NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Industrial temperature range product for the 15ns speed grade is available as a standard device. 3. Values guaranteed by design, not currently tested. 4. tSKEW2 applies to synchronous PAE and synchronous PAF only. Com’l & Ind’l(2) IDT72V805L15 IDT72V815L15 IDT72V825L15 IDT72V835L15 IDT72V845L15 Min. Max. 66.7 — 2 10 15 — 6— 6— 4— 1— 4— 1— 15 — 10 — 10 — — 15 0— 38 38 — 10 — 10 — 20 — 10 — 20 — 10 — 20 — 10 6.5 — 5— 6— 18 — Commercial IDT72V805L20 IDT72V815L20 IDT72V825L20 IDT72V835L20 IDT72V845L20 Min. Max. 50 MHz 2 12 20 — 8— 8— 5— 1— 5— 1— 20 — 12 — 12 — — 20 0— 3 10 3 10 — 12 — 12 — 22 — 12 — 22 — 12 — 22 — 12 8— 8— 8— 20 — 3.3V 330Ω Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1 5 D.U.T. 510Ω 30pF* 4295 drw 03 Figure 1. Output Load * Includes jig and scope capacitances. 5 Page IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES WRITE EXPANSION OUT/HALF-FULL FLAG (WXOA/HFA, WXOB/HFB) This is a dual-purpose output. In the Single Device and Width Expansion mode, when Write Expansion In (WXIA/WXIB) and/or Read Expansion In (RXIA/RXIB) are grounded, this output acts as an indication of a half-full memory. After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full flag goes LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full flag (HFA/ HFB) is then reset to HIGH by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is asynchronous. In the Daisy Chain Depth Expansion mode, WXI is connected to WXO of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device writes to the last location of memory. READ EXPANSION OUT (RXOA/RXOB) In the Daisy Chain Depth Expansion configuration, Read Expansion In (RXIA/RXIB) is connected to Read Expansion Out (RXOA/RXOB) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device reads from the last location of memory. DATA OUTPUTS (Q0-Q17, QB0-QB17) Q0-Q17 are data outputs for 18-bit wide data. 11 11 Page

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