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PDF IDT72V71643 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V71643 | |
| Descripción | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING | |
| Fabricantes | Integrated Device Tech | |
| Logotipo |  |
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3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE
MATCHING
4,096 x 4,096
IDT72V71643
FEATURES:
• Up to 32 serial input and output streams
• Maximum 4,096 x 4,096 channel non-blocking switching
• Accepts data streams at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s
• Rate matching capability: Mux/Demux mode and Split mode
• Output Enable Indication Pins
• Per-channel Variable Delay mode for low-latency applications
• Per-channel Constant Delay mode for frame integrity applications
• Automatic identification of ST-BUS® and GCI serial streams
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high-impedance output control
• Per-channel Processor mode to allow microprocessor writes to
TX streams
• Direct microprocessor access to all internal memories
• Memory block programming for quick setup
• IEEE-1149.1 (JTAG) Test Port
FUNCTIONAL BLOCK DIAGRAM
• Internal Loopback for testing
• Available in 144-pin Thin Quad Flatpack (TQFP) and
144-pin Ball Grid Array (BGA) packages
• Operating Temperature Range -40°C to +85°C
• 3.3V I/O with 5V tolerant inputs and TTL compatible outputs
DESCRIPTION:
The IDT72V71643 has a maximum non-blocking switch capacity of
4,096x4,096channelswithdatarates at 2.048Mb/s,4.096Mb/s,8.192 Mb/s
or 16.384 Mb/s. With 32 inputs and 32 outputs, a variety of rate combinations
is supported, under either Mux/Demux mode or Split mode, to allow for
switching between streams of different data rates.
Output enable indications are provided through optional pins (one pin per
output stream, only 16 output streams can be used in this mode) to facilitate
external data bus control.
For applications requiring 32 streams and 32 per-stream Output Enable
indicators, there is also an All Output Enable Feature.
Vcc GND RESET
TMS TDI TDO TCK TRST
ODE
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
Receive
Serial Data
Streams
Timing Unit
Test Port
Loopback
Data Memory
Output
MUX
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
Microprocessor Interface
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
TX16/OEI0
TX17/OEI1
TX18/OEI2
TX19/OEI3
TX20/OEI4
TX21/OEI5
TX22/OEI6
TX23/OEI7
TX24/OEI8
TX25/OEI9
TX26/OEI10
TX27/OEI11
TX28/OEI12
TX29/OEI13
TX30/OEI14
TX31/OEI15
CLK F0i FE/ WFPS DS CS R/W A0-A14 DTA D0-D15
HCLK
5902 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS® is a trademark of Mitel Corp.
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2002
DSC-5902/6
1 page  
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
The IDT72V71643 is capable of switching up to 4,096 x 4,096 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per channel basis.
The serial input streams (RX) and serial output streams (TX) of the
IDT72V71643 can be run up to 16.384 Mb/sallowing 256 channels per125µs
frame. Depending on the input and output data rates the device can support
up to 32 serial streams.
With two main operating modes, Processor mode and Connection Mode,
the IDT72V71643 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
controlandstatusinformationiscriticalindatatransmission,theProcessormode
is especially useful when there are multiple devices sharing the input and output
streams.
With three main configuration modes, Regular, Mux/Demux, and Split mode
the IDT72V71643 is designed to work in a mixed data-rate environment. In
Mux/Demux mode, all of the input streams work at one data rate and the output
streamsatanother. Dependingontheconfiguration,moreorlessserialstreams
will be available on the inputs or outputs to maintain a non-blocking switch. In
Split Mode, half of the input streams are set at one rate, while the other half are
settoanotherrate. Inthismode,bothinputandoutputstreamsaresymmetrical.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V71643
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles for speeds up
to 8 Mb/s or +2.5 clock cycles for 16 Mb/s. (See Table 8 for maximum allowable
skew).
The IDT72V71643 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in
debugging and ease use of the device without sacrificing capabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory. The Data Memory is only written
by the device from the RX streams and can be read from either the TX streams
or the microprocessor.
DataoutputontheTXstreamsmaycomefromeithertheSerialInputStreams
(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in Connection Memory are used
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor mode, the microprocessor writes data to the Connection Memory
locations corresponding to the stream and channel that is to be output. The lower
byte (8 least significant bits) of the Connection Memory is output every frame
until the microprocessor changes the data or mode of the channel. By using this
Processor mode capability, the microprocessor can access input and output
time-slots on a per channel basis.
The most significant bits of the Connection Memory are used to control per
channel functions such as Processor mode, Constant or Variable Delay mode,
three-state of output drivers, and the Loopback function.
OPERATING MODES
In addition to Regular mode where input and output streams are operating
at the same rate, the IDT72V71643 incorporates a rate matching function in two
different modes: Split mode and Mux/Demux mode. In Split mode some of the
inputstreamsaresetatonerate,whileothersaresettoanotherrate. Bothinput
and output streams are symmetrical. In Mux/Demux mode, all input streams
are operating at the same rate, while output streams are operating at a different
rate. All configurations are non-blocking. These two modes can be entered
by setting the DR3-0 bits in the Control Register, see Table 5.
OUTPUT IMPEDANCE CONTROL
In order to put all streams in three-state, all per-channel three-state control
bits in the Connection Memory are set (MOD0 and MOD1 = 1) or both the ODE
pin and the OSB bit of the Control Register must be zero. If any combination
other than 0-0, for the ODE pin and the OSB bit, is used, the three-state control
ofthestreamswillbelefttothestateoftheMOD1andMOD0bitsoftheConnection
Memory. The IDT72V71643 incorporates a memory block programming
feature to facilitate three-state control after reset. See Table 1 for Output High-
Impedance Control.
SERIAL DATA INTERFACE TIMING
When a 16Mb/s serial data rate is required, the master clock frequency
will be running at 16.384MHz resulting in a single-bit per clock. For all other
cases, 2Mb/s, 4Mb/s, and 8Mb/s, the master clock frequency will be twice the
fastest data rate on the serial streams. Use Table 5 to determine clock speed
and DR3-0 bits in the Control Register to setup the device. The IDT72V71643
provides two different interface timing modes, ST-BUS® or GCI. The
IDT72V71643 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS® or GCI.
In ST-BUS®, when running at 16.384MHz, data is clocked out on the
falling edge and is clocked in on the subsquent rising-edge. At all other data
rates, there are two clock cycles per bit and every second falling edge of the
master clock marks a bit boundary and the data is clocked in on the rising edge
of CLK, three quarters of the way into the bit cell. See Figure 17 for timing.
In GCI format, when running at 16.384MHz, data is clocked out on the
rising edge and is clocked in on the subsquent falling edge. At all other data
rates, there are two clock cycles per bit and every second rising edge of the
master clock marks the bit boundary and data is clocked in on the falling edge
of CLK at three quarters of the way into the bit cell. See Figure 18 for timing.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.F0i).
Although input data is synchronous, delays can be caused by variable path
serial backplanes and variable path lengths, which may be implemented in large
centralized and distributed switching systems. Because data is often delayed
this feature is useful in compensating for the skew between clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 7). The frame offset shown is a function
of the data rate, and can be as large as +4.5 master clock (CLK) periods forward
with a resolution of ½ clock period. To determine the maximum offset allowed
see Table 8.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V71643 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse F0i. Setting the start
frame evaluation (SFE) bit low for at least one frame starts a measurement cycle.
5
5 Page 
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
TABLE 5 — SWITCH MODES
COMMERCIAL TEMPERATURE RANGE
Switching
Mode
Regular
Mux/Demux
Split
Control Bits
DR3 DR2 DR1 DR0
0 0 00
0 0 01
0 0 10
0 0 11
0 1 00
0 1 01
0 1 10
0 1 11
1 0 00
1 0 01
1 0 10
1 0 11
1 1 00
1 1 01
1 1 10
1 1 11
Data Rate bits/s
Receive Streams
Transmit Streams
2 M on RX0-31
4 M on RX0-31
8 M on RX0-31
16 M on RX0-15
2 M on TX0-31
4 M on TX0-31
8 M on TX0-31
16 M on TX0-15
2 M on RX0-31
8 M on RX0-7
4 M on RX0-31
8 M on RX0-15
16 M on RX0-3
2 M on RX0-31
16 M on RX0-15
8 M on RX0-31
8 M on TX0-7
2 M on TX0-31
8 M on TX0-15
4 M on TX0-31
2 M on TX0-31
16 M on TX0-3
8 M on TX0-31
16 M on TX0-15
2 M on RX0-15;
8 M on RX16-31
2 M on TX0-15;
8 M on TX16-31
2 M on RX0-15;
4 M on RX16-31
2 M on TX0-15;
4 M on TX16-31
4 M on RX0-15;
8 M on RX16-31
4 M on TX0-15;
8 M on TX16-31
8 M on RX0-15;
16 M on RX16-23
8 M on TX0-15;
16 M on TX16-23
Clock Rate
MHz
4
8
16
16
16
16
16
16
16
16
16
16
16
8
16
16
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT72V71643.PDF ] | |
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