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PDF PCM1772RGAR Data sheet ( Hoja de datos )
| Número de pieza | PCM1772RGAR | |
| Descripción | LOW VOLTAGE AND LOW POWER STEREO AUDIO DIGITAL TO ANALOG CONVERTER WITH LINEOUT AMPIIFIER | |
| Fabricantes | Burr-Brown Corporation | |
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BurrĆBrown Products
from Texas Instruments
PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
LOWĆVOLTAGE AND LOWĆPOWER STEREO AUDIO
DIGITALĆTOĆANALOG CONVERTER WITH LINEOUT AMPLIFIER
FEATURES
D Multilevel DAC Including Lineout Amplifier
D Analog Performance (VCC1, VCC2 = 2.4 V):
− Dynamic Range: 98 dB Typ
− THD+N at 0 dB: 0.007% Typ
D 1.6-V to 3.6-V Single Power Supply
D Low Power Dissipation: 6 mW at VCC1,
VCC2 = 2.4 V
D System Clock: 128 fS, 192 fS, 256 fS, 384 fS
D Sampling Frequency: 5 kHz to 50 kHz
D Software Control (PCM1772):
− 16-, 20-, 24-Bit Word Available
− Left-, Right-Justified, and I2S
− Slave/Master Selectable
− Digital Attenuation: 0 dB to –62 dB,
1 dB/Step
− 44.1-kHz Digital De-Emphasis
− Zero Cross Attenuation
− Digital Soft Mute
− Monaural Analog-In With Mixing
− Monaural Speaker Mode
D Hardware Control (PCM1773):
− Left-Justified and I2S
− 44.1-kHz Digital De-Emphasis
− Monaural Analog-In With Mixing
D Pop-Noise-Free Circuit
D 3.3-V Tolerant
D Packages: TSSOP-16 and VQFN-20, Lead Free
APPLICATIONS
D Portable Audio Player
D Cellular Phone
D PDA
D Other Applications Requiring Low-Voltage
Operation
DESCRIPTION
The PCM1772 and PCM1773 devices are CMOS,
monolithic, integrated circuits which include stereo
digital-to-analog converters, lineout circuitry, and
support circuitry in small TSSOP-16 and VQFN-20
packages.
The data converters use TI’s enhanced multilevel ∆-Σ
architecture, which employs noise shaping and
multilevel amplitude quantization to achieve excellent
dynamic performance and improved tolerance to clock
jitter. The PCM1772 and PCM1773 devices accept
several industry standard audio data formats with 16- to
24-bit data, left-justified, I2S, etc., providing easy
interfacing to audio DSP and decoder devices.
Sampling rates up to 50 kHz are supported. A full set of
user-programmable functions are accessible through a
3-wire serial control port, which supports register write
functions.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
1 page  
www.ti.com
Terminal Functions
PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
PCM1772PW
TERMINAL
NAME NO.
AGND1
5
AGND2
6
AIN 10
BCK
3
I/O
—
—
I
I/O
DATA
LRCK
2I
1 I/O
MC 14 I
MD 13 I
MS 15 I
PD 4 I
SCKI
VCC1
VCC2
VCOM
16 I
12 —
11 —
7—
VOUTL
VOUTR
9O
8O
PCM1772RGA
TERMINAL
NAME NO.
I/O
AGND1
4—
AGND2
5—
AIN 10 I
BCK
2 I/O
DATA
LRCK
1I
20 I/O
MC 14 I
MD 13 I
MS 15 I
NC 8, 17, —
18, 19
PD 3 I
SCKI
VCC1
VCC2
VCOM
VOUTR
VOUTL
16 I
12 —
11 —
6—
7O
9O
DESCRIPTIONS
Analog ground. This is a return for VCC1.
Analog ground. This is a return for VCC2.
Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs.
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from external device. In master interface mode, the PCM1772 device generates the BCK output to an external device.
Serial audio data input
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1772 device generates the LRCK output to an external device.
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1772 device.
Mode control port select. The control port is active when this terminal is low.
Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default
settings.
System clock input
Power supply for all analog circuits except the lineout amplifier.
Analog power supply for the lineout amplifier circuits. The voltage level must be the same as VCC1.
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal.
L-channel analog signal output of the lineout amplifiers
R-channel analog signal output of the lineout amplifiers
DESCRIPTIONS
Analog ground. This is a return for VCC1.
Analog ground. This is a return for VCC2.
Monaural analog signal mixer input. The signal can be mixed with output of L- and R-channel DACs.
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from an external device. In the master interface mode, the PCM1772 device generates the BCK output to an external
device.
Serial audio data input
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1772 device generates the LRCK output to an external device.
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1772 device.
Mode control port select. The control port is active when this terminal is low.
No connect
Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default
settings.
System clock input
Power supply for all analog circuits except lineout amplifier.
Analog power supply for lineout amplifier circuits. The voltage level must be the same as VCC1.
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal.
R-channel analog signal output of lineout amplifiers.
L-channel analog signal output of lineout amplifiers.
5
5 Page 
www.ti.com
PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
SUPPLY CURRENT
vs
SAMPLING FREQUENCY
Operational
Power Down
10 20 30 40
fS – Sampling Frequency – kHz
Figure 14
20
18
16
14
12
10
8
6
4
2
0
50
DYNAMIC RANGE
vs
JITTER
100
99
98
97
96
95
94
0
100 200 300 400 500 600 700
Jitter – ps
Figure 15
All specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted.
11
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