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PDF PCM1760P Data sheet ( Hoja de datos )

Número de pieza PCM1760P
Descripción Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM
Fabricantes Burr-Brown Corporation 
Logotipo Burr-Brown Corporation Logotipo



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No Preview Available ! PCM1760P Hoja de datos, Descripción, Manual

® PCM1760P/U
DF1760P/U
Multi-Bit Enhanced Noise Shaping 20-Bit
ANALOG-TO-DIGITAL CONVERSION SYSTEM
FEATURES
q DUAL 20-BIT MONOLITHIC MODULATOR
(PCM1760) AND MONOLITHIC
DECIMATING DIGITAL FILTER (DF1760)
q HIGH PERFORMANCE:
THD+N: –92dB typ, –90dB max
Dynamic Range: 108dB typ
SNR: 108dB min, 110dB typ
Channel Separation: 98dB typ, 94dB min
q 64X OVERSAMPLING
q CO-PHASE CONVERSION
q RUNS ON 256fs OR 384fs SYSTEM
CLOCK
q VERSATILE INTERFACE CAPABILITY:
16-, 20-Bit Output
MSB First or LSB First Format
q OPTIONAL FUNCTIONS:
Offset Error Calibration
Overflow Detection
Power Down Mode (DF1760)
q RUNS ON ±5V SUPPLIES (PCM1760) AND
5V SUPPLY (DF1760)
q COMPACT 28-PIN PACKAGES:
28-Pin DIP and SOIC
DESCRIPTION
The PCM1760 and DF1760 combine for a low-cost,
high-performance dual 20-bit, 48kHz sampling ana-
log-to-digital conversion system which is specifically
designed for dynamic applications.
The PCM1760/DF1760 pair form a 4-bit, 4th order,
64X oversampling analog-to-digital converter.
The PCM1760 is a delta-sigma modulator that uses a
4-bit quantizer within the modulation loop to achieve
very high dynamic range.
The DF1760 is a high-performance decimating digital
filter. The DF1760 accepts 4-bit 64fs data from the
PCM1760 and decimates to 20-bit 1fs data.
The FIR filter of the DF1760 has pass-band ripple of
less than ±0.001dB and greater than 100dB of the
reject band attenuation.
PCM1760
DF1760
Analog
Input (L)
Analog
Input (R)
4 Stage, 4-Bit
Delta-Sigma
Modulator
64fs
4 Stage, 4-Bit
Delta-Sigma
Modulator
Timing
Control
and
Interface
64fs
256fs
1/16 4fs
FIR
Filter
Filter
fs
Timing
Control
and
Interface
Data
System
Clock
256/384fs
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1993 Burr-Brown Corporation
PDS-1174C
Printed in U.S.A. July, 1994

1 page




PCM1760P pdf
BLOCK DIAGRAM OF PCM1760
RCH, VIN
RIN1R
C1R
C2R
C3R
C4R
4
In-1R
RT1R
RIN2R
3
Out-1R
2
In-2R
RT2R
RZ1R
1
Out-2R
NC
28
+
27
BPODC-R
SERVO
DC
5
+
1R
+5V
+
+
–5V
+
+VCC
6
AGND
7
–VCC
8
Sub
BGDC
9
Band Gap
Bias
Servo
Amp
S/HINR
RCH
2R S/H
IOUTR
IOUTR
RCH
BPO
RCH
DAC
RCH
ADC
IOUTL
IOUTL
LCH
DAC
LCH
BPO
LCH
ADC
D3
26
D2
25
D
e
D1
c 24
o D0
d
e 23
r +VDD
22
DGND
T 21
i
m
–VDD
i 20
n 256fs
g 19
C
T Strobe
L 18
L/R CK
17
+5V
+
+
–5V
NC
10
1L
LCH
2L
S/HINL
S/H
LCH, VIN
In-1L
11
Out-1L
12
In-2L Out-2L
13 14
NC
15
RIN1L
RIN2L
RZ1L
BPODC-L
16
+
C1L C2L
RT1L
C3L C4L
RT2L
External Components Condition
RIN 1R/L C1, C2 R/L
2.2k2200pF
C3, C4 R/L RT2 R/L
1800pF 560
RTIR/L
470
RZ1 R/L
1.2k
RIN 2R/L
1.3k
5 PCM1760P/U DF1760P/U
®

5 Page





PCM1760P arduino
OUTPUT TONE ELIMINATION
When the sampling frequency (fs) is between 40kHz and 50 kHz
and the L/R relative offset voltage (Vs) is less than or equal to
0.05% of full scale range, the PCM1760 may output a tone
similar to an idle tone. This tone is very low and its frequency
depends on the input L/R relative offset voltage, Vs. This
tone never occurs when the sampling frequency (fs) is 32kHz.
To avoid this tone, the offset voltage should be summed
using an amplifier, buffer, active low pass filter, etc., to
cause the input L/R relative offset voltage (Vs) to be
greater than 0.05% of full scale range.
It is recommended that:
(A) Sum offset at both L/R channels
Lch: VIL = –20mV ±10%
Rch: VIR = +10mV ±10%
(B) Sum offset at L channel
Lch: VIL = –30mV ±10%
Rch: VIR = ±1mV (by a precircuit)
When FSR = 5V (±2.5V).
Figure 8 shows an application circuit for summing the offset
at both L/R channels.
Alternately, Figure 9 shows an application circuit for use
when fs = 48kHz which changes the external integrator
circuit of the PCM1760.
MODULATOR COMPONENTS
AND SAMPLING FREQUENCY
The PCM1760/DF1760 are capable to 30kHz to 50kHz fs
sampling frequency by condition with external components
value which are shown in Basic Connection Diagram.
The characteristics of the modulator’s integrator can be set
by external components. The values in the block diagram on
page five are recommended for optimized performance.
Low leakage, low voltage coefficient capacitors are recom-
mended for integration capacitors.
The tolerance of external components should be better than ±2%.
RIN1-L 11
2.2k
VIL = –20mV ±10%
PCM1760
RIN1-R 4
2.2k
VIR = +10mV ±10%
FIGURE 8. Application Example to Eliminate the Tone
(offset voltage implementation for both chan-
nels).
OFFSET ERROR CALIBRATION
The offset voltage of the PCM1760 and the input stage of
the system can be compensated by using the calibration
mode of the DF1760. Offset calibration is shown in Figure
10. An optional analog switch is driven by a CAL output of
the DF1760. The PD input of the DF1760 is used to initiate
the calibration cycle.
ANALOG INPUT AND DIGITAL OUTPUT
Ideal output digital code range for 20-bit resolution is from
8000H (–Full Scale) to 7FFFFH (+Full Scale).
The DF1760, combined with 70000H (±FSR) of the
PCM1760, produces a digital output code range at ±FSR
input of 90000H (–FSR).
The relationship between analog input and digital output is
shown in Table I.
C1 C2
C3 C4
RIN1 = 2.2k
RT2 = 2.2k
C1, C2, C3, C4 = 1200pF
RT1 = 470
RZ1 = 470
CZ1 = 220pF
RIN2 = 1.3k
RZ2 = 910
RIN1
RT1 RZ1
CZ1
RIN2
11 12 13
RT2 RZ2
14
OP1
PCM1760
OP2
FIGURE 9. Application Example to Eliminate the Tone (alternative modulator's integrator circuit. Only for fs = 48kHz).
11 PCM1760P/U DF1760P/U
®

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