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PDF PCM1750P Data sheet ( Hoja de datos )
| Número de pieza | PCM1750P | |
| Descripción | Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PCM1750P (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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® PCM1750P
PCM1750U
Dual CMOS 18-Bit Monolithic Audio
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q DUAL 18-BIT LOW-POWER CMOS AUDIO
A/D CONVERTER
q FAST 4.5µs MIN CONVERSION TIME
INCLUDING S/H
q VERY LOW MAX THD+N: –88dB Without
External Adjust
q COMPLETE WITH INTERNAL
REFERENCE AND DUAL S/H FUNCTION
q TWO CO-PHASE SAMPLED, ±2.75V
AUDIO INPUTS
q CAPABLE OF 4X PER CHANNEL
OVERSAMPLING RATE
q RUNS ON ±5V SUPPLIES AND
DISSIPATES 300mW MAX
q COMPACT 28-PIN PLASTIC DIP OR SOIC
DESCRIPTION
The PCM1750 is a low cost, dual 18-bit CMOS
analog-to-digital converter optimized for dynamic sig-
nal applications. The PCM1750 features true co-phased
inputs with an internal sample/hold function for each
channel. The PCM1750 also comes complete with an
internal reference. Total power dissipation is less than
300mW max using ±5V voltage supplies. Low maxi-
mum Total Harmonic Distortion + Noise (–88dB max)
is 100% tested. The very fast PCM1750 is capable
of 4X x audio bandwidth oversampling rates on both
input channels simultaneously, providing greater free-
dom to designers in selecting input anti-aliasing fil-
ters.
PCM1750 outputs serial data in a format that is com-
patible with many digital filter chips and comes pack-
aged in a space saving 28-pin plastic DIP or SOIC.
MSB Adj Left
Offset Adj Left
VIN Left
S OUT Left
SOUT Right
VIN Right
Offset Adj Right
MSB Adj Right
CDAC
S/H Left
CDAC
S/H Right
Reference
Comp
18-Bit SAR
Latch
Latch
Shift Register
Control Logic
Comp
18-Bit SAR
Reference
Clock
Convert
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-11084B
PPCrintMed i1n 7U.5S.A0. October, 1993
®
1 page  
TYPICAL PERFORMANCE CURVES (CONT)
At 25°C, and ±VA; +VD = ±5V, unless otherwise noted. Where relevant, specifications apply to both left and right input-output channels.
0
–25
–50
–75
–100
–125
–150
0
FFT 20kHz (24kHz BW; 2048 POINTS)
5 10 15
Frequency (kHz)
20 24
FFT 17kHz and 21kHz (24kHz BW; 16384 POINTS)
0
–6dB
–25
–50
–75
–100
–125
–150
0
5 10 15
Frequency (kHz)
20 24
0
–25
–50
–75
–100
–125
–150
0
FFT 3.7kHz (96kHz BW; 2048 POINTS)
20 40 60
Frequency (kHz)
80 96
0
–25
–50
–75
–100
–125
–150
0
FFT 52kHz (96kHz BW; 2048 POINTS)
20 40 60
Frequency (kHz)
80 96
0
–25
–50
–75
–100
–125
–150
0
FFT 92kHz (96kHz BW; 2048 POINTS)
20 40 60
Frequency (kHz)
80 96
FFT 88kHz and 92kHz (96kHz BW; 16384 POINTS)
0 –6dB
–25
–50
–75
–100
–125
–150
0
20 40 60
Frequency (kHz)
80 96
®
5 PCM1750
5 Page 
can be used to purposely alias a band-limited signal down
into the baseband of the converter. This technique is called
undersampling and can be used to directly down-convert an
intermediate frequency riding on a much higher carrier
frequency.
DIGITAL I/O AND TIMING
Input/Output Logic Compatibility
Digital logic on the PCM1750 is CMOS compatible. Digital
outputs on the PCM1750 are capable of driving a minimum
of two standard TTL input loads.
Digital output coding is in binary two’s complement. Table I
gives the precise input/output voltage/code relationships for
the PCM1750. Figure 5 shows these same relationships in a
graphical format.
Convert Command and External Clock Input
A conversion is initiated on its positive going edge of the
convert command. Although the convert command can re-
turn low at any time (prior to 50ns before the rising edge of
the 19th clock), a typical convert command pulse width of
81ns (as called out in Figure 3) is specified for a 192kHz
sample rate (fS). The reason for a pulse width spec is to
reduce problems associated with digital logic feedthrough
noise. The return of convert command to a logic low level in
the specified time interferes least with the successive ap-
proximation process. Also, it should be noted that putting
fast logic edges (<5ns) on convert command (P11) and the
external clock input (P4) may cause logic feedthrough to the
analog stages in the converter and will result in added
distortion during the sampling and conversion process.
Using the optional DF1750 digital filter provides adequately
slow transitions to maintain full specification performance.
If necessary, an external RC, on the convert command line
may be used to slow fast logic edges.
As with the convert command, the external clock input is
positive edge triggered and is not duty-cycle dependent
other than to improve digital feedthrough noise immunity. A
50% duty cycle clock can be used instead of 33% if desired.
Refer to Figure 3 for recommended timing relationships.
Regardless of what clock duty cycle is used, all operations
relating to valid data clocking should be synchronized to the
rising edge of the clock input.
Although there is a maximum conversion time called out in
the specification table, the PCM1750 can have a consider-
ably longer conversion cycle. Droop of the internal capaci-
tors will ultimately determine what the true maximum
conversion time can be. The min/typ/max times shown in
Figure 3 are based on minimum sample rate of 48kHz, a
typical of 192kHz, and a maximum of 222kHz. All specifi-
cations are tested at 192kHz. The minimum sample rate
assumption is based on clock periods that increase as time
between convert commands increases. Any sample rate
down to near DC can be utilized by observing maximum
clock cycle requirements and spacing convert commands to
achieve lower sample rates. This means that the time interval
T2 shown in Figure 3 does not have a maximum value.
Clock Lockout
Any number of clocks can be given to the PCM1750 beyond
the 19 required for normal operation. If a continuous clock
is used, all clocks beyond the 19th are gated off by the
PCM1750’s internal logic until the next positive going edge
of the convert command. The converter also goes into the
sample (track) mode starting on the positive edge of the 19th
clock until the next positive edge of the convert command,
regardless of how many additional clocks are offered. The
ideal operation of the converter stops the clock input after
the 19th during this critical signal acquisition time. This is
the timing shown in Figure 3 . The critical timing aspect that
must be observed if a clock input other than the recom-
mended is used, is that ample time following the positive
edge of convert command proceed the next rising clock
edge. If this time is shortened, the most important bit-1
(MSB) decision, which is finalized on the first clock edge
after convert command, will be adversely affected. In other
words, the clock input cannot have a rising edge during the
time interval T3 shown in Figure 3.
SIGNAL-TO-NOISE RATIO
Another specification for A/D converters is signal-to-noise
ratio (SNR). For this measurement, a full-scale 1kHz signal
is applied and the sampling rate of the PCM1750 is set at
192kHz. An FFT is performed on the digital output and the
noise power in the non-harmonic audio-bandwidth frequency
bins (20Hz to 24kHz) is summed and expressed in relation
to the full-scale input signal.
One advantage of using the PCM1750 in this oversampled
mode with the optional DF1750 digital decimation filter is
that the converter noise is spread over the full 0Hz to 96kHz
passband and then suppressed by the digital filter stopband
attenuation (from 24kHz to 96kHz). This effectively in-
creases the SNR of the PCM1750 by 6dB when it is used as
an audio bandwidth converter. The other advantage is that
the need for a higher-order anti-aliasing input filtering is
greatly reduced.
THD + N
The key specification for the PCM1750 is total harmonic
distortion plus noise (THD+N). In terms of signal measure-
ment, THD+N is the ratio of DistortionRMS + NoiseRMS /
SignalRMS expressed in dB. For the PCM1750, THD+N is
100% tested at all three specified input levels using the
production test setup shown in Figure 6. For this measure-
ment, as with the SNR test, a full-scale 1kHz signal is
applied and the sampling rate of the PCM1750 is set at
192kHz (which is 4X the standard digital audio sample rate
of 48kHz). An FFT is performed on the digital output and
the total power in all audio-bandwidth frequency bins (20Hz
to 24kHz) is summed and expressed in relation to the full-
scale input signal.
For the audio band, the THD+N of the PCM1750 is essen-
tially flat for all frequencies and input signal levels. In the
Typical Performance Curves THD+N versus Frequency
®
11 PCM1750
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet PCM1750P.PDF ] | |
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