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PDF PCM1740E Data sheet ( Hoja de datos )

Número de pieza PCM1740E
Descripción Stereo Audio DIGITAL-TO-ANALOG CONVERTER with VCXO and PLL
Fabricantes Burr-Brown Corporation 
Logotipo Burr-Brown Corporation Logotipo



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®
PCM1740
PCM1740
For most current data sheet and other product
information, visit www.burr-brown.com
TM Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
with VCXO and PLL
FEATURES
DESCRIPTION
q COMPLETE DELTA-SIGMA STEREO DAC
The PCM1740 is a complete stereo audio digital-to-analog
q VOLTAGE-CONTROLLED CRYSTAL
OSCILLATOR: 27MHz ±150ppm Output with
0V to 3V Input
q PROGRAMMABLE PLL
256fS or 384fS Audio System Clock Output
q DYNAMIC PERFORMANCE:
Dynamic Range: 94dB
SNR: 94dB
THD+N: –89dB
q SAMPLING FREQUENCIES:
16kHz, 22.05kHz, 24kHz
converter with on-chip PLL and VCXO. The PCM1740 is
designed specifically for set-top box applications requiring
high-quality audio playback, a precision tuned 27MHz mas-
ter clock source, and support for multiple audio-sampling
frequencies.
The stereo D/A converter utilizes multi-bit, delta-sigma
architecture, which includes an 8x interpolation filter, third-
order noise shaping, 5-level amplitude quantization, and an
analog low-pass filter. The PCM1740 includes a number of
user-programmable functions, which are accessed via a
standard I2C-Bus interface.
32kHz, 44.1kHz, 48kHz
64kHz, 88.2kHz, 96kHz
APPLICATIONS
q SERIAL AUDIO INTERFACE:
q SET-TOP BOXES
Standard or I2S Data Formats
q DIGITAL BROADCAST RECEIVERS
16-, 20-, or 24-Bit Data
q I2C-BUS® INTERFACE FOR CONTROL
REGISTERS(1):
Slave Receiver Operation
7-Bit Addressing
Standard Transfer Rate (up to 100kbps)
q PROGRAMMABLE CONTROLS:
Digital Attenuation (256 steps)
Soft Mute
Infinite Zero Detect Mute
De-Emphasis (32kHz, 44.1kHz, 48kHz)
DAC Output Mode
q SINGLE +5V SUPPLY
q SMALL SSOP-24 PACKAGE
BCK
LRCK
DATA
SCL
SDA
AD1
AD0
XTUN
27MHz
Crystal
XT1
XT2
RST
PCM
Audio
I/F
I2C
I/F
and
REGs
VCXO
8x
Oversampling
Digital Filter
and
Sub-Functions
Process
DAC
(L)
DAC
(R)
Low-Pass
Filter
and Amp
Counter N
Counter M
Phase
Detector
LPF
VCO
Reset
Power Supply
VOUTL
VCOM
VOUTR
ZERO
SCKO
(256fS/ 384fS)
MCKO
(27MHz)
VPP PGND VCC AGND VDD DGND
NOTE: (1) I2C-Bus® is a registered trademark of Philips Semiconductor.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 2000 Burr-Brown Corporation
PDS-11551A
PPrCinteMd in1U7.S4.A0. February, 2000
®

1 page




PCM1740E pdf
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, FSCKO = 384fS = 16.9344MHz, and 16-bit data, unless otherwise noted.
0
–20
–40
–60
–80
–100
0
FREQUENCY RESPONSE
(De-emphasis OFF, fS = 44.1kHz)
123
fS
4
0
–0.2
–0.4
–0.6
–0.8
–1
0
PASSBAND RIPPLE
(De-emphasis OFF, fS = 44.1kHz)
0.1 0.2 0.3 0.4
fS
0.5
0
–2
–4
–6
–8
–10
–12
0
DE-EMPHASIS FREQUENCY RESPONSE (3kHz)
5k 10k 15k 20k 25k
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
0
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
5k 10k 15k 20k 25k
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
0
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
5k 10k 15k 20k 25k
Frequency (Hz)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
DE-EMPHASIS ERROR (3kHz)
3628
7256
Frequency (Hz)
10884
DE-EMPHASIS ERROR (44.1kHz)
14512
4999.8375 9999.675 14999.5125
Frequency (Hz)
DE-EMPHASIS ERROR (48kHz)
19999.35
5442
10884
Frequency (Hz)
16326
21768
®
5 PCM1740

5 Page





PCM1740E arduino
LRCKIN
BCKIN
DIN
tBCH
tBCL
tBCY
tDS
tBL
tDH
tLB
1.4V
1.4V
1.4V
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
BCKIN Rising Edge to LRCIN Edge
LRCIN Edge to BCKIN Rising Edge
DIN Set-up Time
DIN Hold Time
: tBCY
: tBCH
: tBCL
: tBL
: tLB
: tDS
: tDH
: 100ns (min)
: 50ns (min)
: 50ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
FIGURE 10. Audio Interface Timing.
Loss of Synchronization
Ideally, LRCK and BCK will be derived from the SCKO
output, ensuring synchronous operation. For other cases, the
PCM1740 includes circuitry to detect loss of synchroniza-
tion between the LRCK and the system clock, SCKO. A loss
of synchronization condition is detected when the phase
relationship between SCKO and LRCK exceeds ±6 BCK
cycles during one sample period, or 1/fS. If a loss of
synchronization condition is detected, the DAC operation
will halt within one sample period and the analog outputs
will be forced to VCC/ 2 until re-synchronization between
LRCK and SCKO is completed. Figure 11 shows the state of
the analog outputs given a loss of synchronization event.
During the undefined states, as well as transitions between
normal and undefined states, the analog outputs may gener-
ate audible noise.
USER PROGRAMMABLE FUNCTIONS
The PCM1740 includes a number of programmable func-
tions, which are configured using five control registers.
These registers are accessed using the I2C-Bus interface.
State of
Synchronization
Synchronous
Asynchronous
within
1/ fS
VOUT
Undefined Data
Normal
VCOM
(= 0.5 VCC)
Synchronous
22.2 / fS
Undefined
Data
Normal
FIGURE 11. Loss of Synchronization and Analog Output State.
This section describes the control registers, while the
I2C-Bus interface is described in a later section. Table II lists
the available functions and their corresponding reset default
condition.
Register Map
The control register map is shown in Table III. Sub-address
bits B8 through B10 are used to specify the register that is
being written. All reserved bits, shown as “res”, must be set
to ‘0’.
Register Descriptions
The following pages provide detailed descriptions of the five
control registers and their associated functions. All reserved
bits, shown as “res”, must be set to ‘0’.
FUNCTION
Audio Data Format Select:
Standard Format /I2S Format
Audio Data Word Select:
16-Bit /20-Bit /24-Bit
Polarity of LR-clock Selection
De-emphasis Control:
OFF, 32kHz, 44.1kHz, 48kHz
Soft Mute Control
Attenuation Data for Left-channel
Attenuation Data for Right-channel
Attenuation Data Mode Control
Analog Output Mode Select
Infinity Zero Detect Mute Control
DACs Operation Control
System Clock Select: 256fS /384fS
Sampling Frequency Select:
32kHz Group, 44.1kHz Group, 48kHz Group
Sampling Frequency Multiplier:
Normal/ Double/ Half
MODE BY DEFAULT
Standard Format
16-Bit
Left/Right = HIGH/LOW
OFF
OFF
0dB
0dB
Left-channel, Right-channel Individually
Stereo Mode
OFF
ON
384fS
44.1kHz Group
Normal, x1
TABLE II. User-Programmable Functions.
SUB ADDRESS BYTE
REGISTER
Register 0
Register 1
Register 2
Register 3
Register 4
B15 B14 B13 B12 B11 B10
res res res res res A2
res res res res res A2
res res res res res A2
res res res res res A2
res res res res res A2
TABLE III. Control Register Map.
B9 B8
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
11
DATA BYTE
B7
AL7
AR7
PL3
SF1
res
B6
AL6
AR6
PL2
SF0
res
B5 B4
AL5 AL4
AR5 AR4
PL1 PL0
DSR1 DSR0
res res
B3
AL3
AR3
IW1
SYS
res
B2
AL2
AR2
IW0
ATC
OPE
B1
AL1
AR1
DEM
LRP
IZD
B0
AL0
AR0
MUT
IIS
LD
PCM1740
®

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