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PDF PCM16C00 Data sheet ( Hoja de datos )
| Número de pieza | PCM16C00 | |
| Descripción | Configurable Multiple Function PCMCIA Interface Chip | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 1994
PCM16C00
Configurable Multiple Function PCMCIA Interface Chip
General Description
National’s PCM16C00 acts as a standard interface between
the PCMCIA bus and card-side local bus for I O and memo-
ry PCMCIA cards This device allows the card designer to
focus on the design of the dual I O functions while providing
a one-chip solution for I O memory window control concur-
rent interrupt control EEPROM interfacing and power man-
agement In addition to being configurable to interface to
any two ISA compatible I O functions the PCM16C00 sup-
ports logic necessary to simplify a design that uses the Na-
tional DP83902A ST-NIC Ethernet Controller as one of the
functions
The PCM16C00 is fully compliant with PCMCIA version 2 1
and is compatible with serial 4-kbit and 16-kbit EEPROMs
with 8-bit and 16-bit organizations that use the MICROW-
IRETM protocol This multi-function interface IC allows the
system software to setup I O decode windows and provides
the Attribute memory decode control that allow attribute
read and write data transfers
Features
Y PCMCIA Bus Interface
Y Compliant with multi-function extension to PCMCIA
Standards 3 X
Y PCMCIA version 2 1 configuration registers
Y Serial EEPROM interface compatible with MICROWIRE
EEPROM protocol
Y 2-kbyte on chip RAM for attribute memory which shad-
ows the CIS and is used for loading static registers
Y Address decoding and control for 2 I O functions
Y Logic to support any two interrupt capable I O func-
tions on a PCMCIA card
Y Power management and clock control
Y Programmable arbitration unit for PCMCIA host and two
functions
Y Common memory logic
Y National DP83902A Ethernet LAN support logic
Y 4 Bit direction programmable generic digital port
Y ISA-like interface to card function
1 0 System Diagram
FIGURE 1-1
TL F 11669 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11669
RRD-B30M75 Printed in U S A
1 page  
3 0 Pinout Description (Continued)
TABLE 3-2 Serial EEPROM Interface Pins
Pin
Name
EEDO
Pin Pin
Level
Type No Compatibility
I 119 TTL
Internal
Resistor
Description
Serial Data in from EEPROM
EEDI
O 120 CMOS 6 mA
Serial Data out to EEPROM
EECS
EESK
O 122 CMOS 6 mA
O 121 CMOS 6 mA
EEPROM Chip Select
EEPROM Clock Freq e MCLK(0) 32
EESize
I 117 TTL
l100k to VCC EEPROM Size If high the EEPROM size is 16-kbit else the
size is 4-kbit
EEORG I 118 TTL
l100k to VCC EEPROM Organization pin If high the EEPROM is organized
as 16-bit words else organization is 8 bits
Note The Enable EEPROM function is performed in software by writing to the EEPROM Control Register The Enable EEPROM bit will default to low (disabled)
upon power on
Pin
Name
LDATA(15 0)
DPORT(3 0)
EARD
SPK IN
RI IN(0)
RI IN(1)
CIORD
CIOWR
CWAIT(1 0)
CS(1 0)
BHE
READY(1 0)
CINT(1 0)
SRESET(1 0)
Pin
Type
IO
IO
O
I
I
I
O
O
I
O
O
I
I
O
Pin
No
13 – 7
5–1
144 – 141
20 19
18 17
128
127
53
129
23
22
140 64
139 63
21
136 60
138 62
137 61
TABLE 3-3 Card-Side Interface Pins
Level
Compatibility
Internal
Resistor
Description
TTL 6 mA
Hold Circuit
(Note 1)
Card-side Data Bus
TTL 6 mA
CMOS 6 mA
TTL Schmitt
TTL Schmitt
TTL Schmitt
CMOS 6 mA
CMOS 6 mA
TTL
CMOS 6 mA
CMOS 6 mA
TTL
TTL Schmitt
CMOS 6 mA
l100k to VCC
Generic Direction programmable function port for
additional user signals In LAN Mode these signals are
assigned specific meaning for use with an Ethernet LAN
IC
Chip select for external attribute memory not shadowed
in PCM16C00 IC
Input Audio Signal
Ring Indicator for function 0 In LAN Mode this is a
packet indicator input
Ring Indicator for function 1
I O read signals are passed through from HIORD
according to the expression shown below when a valid
address is decoded
(CIORD e HIORD a REG a (CE1 CE2 )
I O write signals are passed through from HIOWR
according to the expression shown below when a valid
address is decoded
CIOWR e HIOWR a REG a (CE1 CE2 )
Card-side transaction wait state inputs
Chip select for each function
Byte high enable When de-asserted and CS( )
asserted an 8-bit access on LDATA(7 0) is in progress
This holds for both odd and even addresses When
asserted and CS( ) asserted a 16-bit access on
LDATA(15 0) is in progress
Indicates that the function is either READY or EREADY
(i e - Busy) This signal is used to assert the Rdy Bsy
bit in Pin Replacement Registers
Card-side interrupt input signals
Signals reset to Card-side functions
5
5 Page 
5 0 Functional Description (Continued)
Arbiter Priority Register
0x03EC
This register controls the priority (from the set
00 01 10 11 ) for each possible card-bus master from the
set PCMCIA Host Function 0 Function 1 The value of
3 is the highest priority whereas 0 is the lowest priority
D7
ArbiterCLK
D6
PreemptEnb
D5 – D4
PCMCIA Host
Priority
D3 – D2
Function 1
Priority
D1 – D0
Function 0
Priority
ArbiterCLK This bit is set to one (1) to increment the Arbi-
ter Latency Register using MCLK(0) 16 This bit is set to
zero (0) to increment the Arbiter Latency Register using
MCLK(0) 1
PreemptEnb If this bit is set to one (1) the arbiter will
allow pre-emption of bus masters If this bit is set to zero (0)
the arbiter will allow a bus master to complete before grant-
ing the bus to another master as determined by the priority
scheme used
Arbiter Latency Register
0x03EE
This register programs a latency timer such that when a
card-bus master is in control of the bus and another unit
requests and wins access to the bus (following priority
scheme) the timer will allow the current bus owner to retain
the bus until the timer expires This is useful when pre-emp-
tions are allowed using the PreemptEnb bit in the Arbiter
Priority Register The timer does not start counting down
until the arbiter queues another device for bus ownership
D7-D0
N e Arbiter Latency Timer Value
Arbiter Latency Timer Value (N) This value is used by an
arbiter counter Therefore the latency time until the
BREQ( ) is relinquished (or internal host BREQ) when
PreemptEnb is set to one (1) is
Latency Time e 16(N) fMCLK(0) when ArbiterCLK e (1)
Latency Time e (N) fMCLK(0) when ArbiterCLK e (0)
Miscellaneous Register
0x03F0
D7
FastEE
D6
LA TRI Func1
D5
LA TRI Func0
D4 – D0
EEPROMStartAddr
FastEE If this bit is set to one (1) then the clock used to
access the EEPROM shall be MCLK(0) 2 If this bit is set to
zero (0) the clock used to access the EEPROM shall be
MCLK(0) 32
LA TRI Func1 LA TRI Func0 This bit should be
set to one (1) when a bus master function will multiplex
address and data on the LDATA( ) bus and will use ADS to
strobe the address phase on this bus to the LADDR( ) bus
In this case the PCM16C00 will drive the LADDR( ) bus and
latch the LDATA( ) bus to the LADDR( ) bus on an ADS
strobe This bit should be set to a zero (0) when a bus
master function will drive the LADDR( ) bus directly In this
case the PCM16C00 will TRI-STATE (not drive) the
LADDR( ) bus when it is granted to function 0 or function 1
in expectation that the function will control the LADDR( )
bus
EEPROMStartAddr This field contains a starting address
for EEPROM read or write access This is ordinarily set to
zero and is used for debug test purposes
Digital Port Direction Register
0x03F2
This register is a read write register that controls the direc-
tion for each individual bit in the Digital Port Register
D7 – D4
Reserved
D3
DPDIR3
D2
DPDIR2
D1
DPDIR1
D0
DPDIR0
DPDIR3 2 1 0 DPDIRi defines the direction of the corre-
sponding DPORT(i) pin and hence the direction of the
DPORTi bit in the Digital Port Register If DPDIRi is set to
zero (0)(default) then the DPORT(i) pin is a digital input If
DPDIRi is set to one (1) then the DPORT(i) pin is a digital
output
Digital Port Register
0x03F4
The Digital Port Register is a read write register connected
to the DPORT(3 0) pins of the PCM16C00 chip Each bit is
direction programmable through software using the Digital
Port Direction Register
D7 – D4
Reserved
D3
DPORT3
D2
DPORT2
D1
DPORT1
D0
DPORT0
DPORT3 2 1 0 If DPDIR is set to one (1) then DPORT may
be written to The value written will be sourced by the corre-
sponding DPORT pin When DPORT is read the value re-
turned will be the last value written to DPORT If DPDIR is
reset to zero (0) then DPORT will assume the value exter-
nally driven into the corresponding DPORT pin Therefore
when DPORT is read it returns the value being driven into
the DPORT pin When written the value is unaffected and
retains the value driven on DPORT
Wait State Timer Register
0x03F6
This register allows the insertion of default wait states from
the PCM16C00 using HWAIT It is intended to be used in
situations where either the function is too slow to respond
with a CWAIT( ) or the unique wait timing constraints be-
tween the system and PC Card design necessitate a default
wait state
D7 – D4
Reserved
D3 – D2
Func1Wait
D1 – D0
Func0Wait
Func1Wait Func0Wait This value is the number (0 1 2
or 3) of MCLK(0) time periods that the PCM16C00 will as-
sert HWAIT during a valid access to a particular function
For Zero wait states program these values to 00b
ID Register
0x1000
This read only register provides the software with IC revision
information
D7 – D3
PCM16C00 Code e 00000b
D2 – D0
Revision Code e 000b
National PCM16C00 Code This code may be used to
identify the PCM16C00 IC The value of this register is
00000b
Revision Code This will uniquely identify the silicon ver-
sion of the PCM16C00 IC as 000b
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCM16C00.PDF ] | |
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