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PDF ZPSD401A2-C-70J Data sheet ( Hoja de datos )

Número de pieza ZPSD401A2-C-70J
Descripción Low Cost Field Programmable Microcontroller Peripherals
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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PSD4XX
ZPSD4XX
Low Cost Field Programmable Microcontroller Peripherals
NOT FOR NEW DESIGN
FEATURES SUMMARY
s Single Supply Voltage:
– 5 V±10% for PSD4XX
– 2.7 to 5.5 V for PSD4XX-V
s Up to 1 Mbit of UV EPROM
s Up to 16 Kbit SRAM
s Input Latches
s Programmable I/O ports
s Page Logic
s Programmable Security
Figure 1. Packages
PLDCC68 (J)
CLDCC68 (L)
TQFP68 (U)
January 2002
This is information on a product still in production but not recommended for new designs.
1/3

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ZPSD401A2-C-70J pdf
PSD4XX Family
1.0
Introduction
(cont.)
2.0
Key Features
2
The PSD4XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be
individually configured to provide many functions, including the following:
MCU I/O
GPLD I/O
Latched address output (for MCUs with multiplexed data bus)
Data bus (for MCUs with non-multiplexed data bus).
The PSD4XX can easily interface with virtually any 8- or 16-bit microcontroller with a
multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the
ZPLDs, enabling the user to generate signals for external devices.
The PSD4XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four
equal-sized blocks. Each block can occupy a different address location, allowing for
versatile address mapping. The access time of the EPROM includes the address latching
and DPLD decoding.
The PSD4XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a
battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a
power failure. Therefore, you can place data in the SRAM that you want to keep after the
power is switched off. Power switchover to the battery automatically occurs when VCC drops
below Vstby.
A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for
microcontrollers with limited address space. The Page Register outputs are connected to
both ZPLDs and thus can also be used for external paging schemes.
The Power Management Unit (PMU) of the PSD4XX enables the user to control the
power consumption on selected functional blocks, based on system requirements.
For microcontrollers that do not generate a chip select input for the PSD, the Automatic
Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down
Mode or Sleep Mode, based on the inactivity of ALE (or AS).
Implementing your design has never been easier than with PSDsoft—ST’s software
development suite. Using PSDsoft, you can do the following:
Configure your PSD4XX to work with virtually any microcontroller
Specify what you want implemented in the programmable logic using a design file
Simulate your design
Download your design to the part using a programmer.
t Single-chip programmable peripheral for microcontroller-based applications
t 256K to 1 Mbit of UV EPROM with the following features:
Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16
Divided into four equally-sized mappable blocks for optimized address mapping
As fast as 70 ns access time, which includes address decoding
Built-in Zero-power technology
t 16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be as
quick as 70 ns, including address decoding. The contents of the SRAM can be
battery-backed by connecting a battery to the Vstby pin. The SRAM also has built-in
Zero-power technology.
t 40 I/O pins (divided into five 8-bit ports) that can be individually configured for:
Standard MCU I/O
PLD/macrocell I/O
Latched address output
High-order address inputs
Special function I/O
Open-drain output

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ZPSD401A2-C-70J arduino
PSD4XX Family
8.0
Table 2.
PSD4XX Pin
Descriptions
8
The following table describes the pin names and pin functions of the PSD4XX. Pins that
have multiple names and/or functions are defined by user configuration.
Pin Name
Pin Function
Type
Function Descriptions
ADIO0 – ADIO15 Address/data bus I/O
RD
WR
CSI
RESET
CLKIN
Multiple Names
1. Read
2. E
3. DS
4. LDS
Multiple Names
1. WR
2. R/W
3. WRL
Chip Select Input
Reset Input
I
I
I
I
Input clock
I
PA0 – PA7
I/O Port A
I/O
PB0 – PB7
I/O Port B
I/O
PC0 – PC7
I/O Port C
I/O
CMOS
or
OD
PD0 – PD7
I/O Port D
I/O
CMOS
or
OD
*Available only in PSD4XXA2 and ZPSD4XXA2 Series.
1. Address/data bus, multiplexed
bus mode
2. Address bus, non-multiplexed
bus mode
Multiple functions
1. Read signal
2. E signal (Clock)
3. Data strobe signal
4. Low byte data strobe
Multiple functions
1. Write signal
2. Read-write signal
3. Low byte write signal
Active low, select PSD4XX
standby mode if high.
Reset I/O ports, ZPLD/macrocells,
and Configuration Registers.
Active low.
Clock input to ZPLD macrocells,
ZPLD Array and APD counter.
Connect to ground if Clock Input
not used.
Multiple functions
1. I/O port
2. ZPLD/macrocell I/O port
3. Latched address outputs
(PA0 – PA7) (A0 – A7)
4. High address inputs (A16 – A23)
Multiple functions
1. I/O port
2. ZPLD/macrocell I/O port
3. Latched address outputs
(PB0–PB7) (A0–A7) or (A8–A15)
Multiple functions
1. I/O port
2. ZPLD input port*
3. Latched address outputs
(PC0 – PC7) (A0–A7)
4. Data Port (D0 – D7,
non-multiplexed bus)
Multiple functions
1. I/O port
2. ZPLD input port*
3. Latched address outputs
(PD0–PD7) (A0–A7) or (A8–A15)
4. Data Port (D8 –D15,
non-multiplexed bus)

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