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PDF PCM1604Y Data sheet ( Hoja de datos )

Número de pieza PCM1604Y
Descripción 24-Bit/ 192kHz Sampling/6-Channel/ Enhanced Multi-Level/ Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
Fabricantes Burr-Brown Corporation 
Logotipo Burr-Brown Corporation Logotipo



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No Preview Available ! PCM1604Y Hoja de datos, Descripción, Manual

® PCM1604
PCM1604
PCM1605
PCM1605
For most current data sheet and other product
information, visit www.burr-brown.com
TM 24-Bit, 192kHz Sampling,6-Channel,
Enhanced Multi-Level, Delta-Sigma
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q PIN COMPATIBLE WITH PCM1600, PCM1601
q 24-BIT RESOLUTION
q ANALOG PERFORMANCE:
Dynamic Range: 105dB typ
SNR: 104dB typ
THD+N: 0.0018% typ
Full-Scale Output: 3.1Vp-p typ
q 8x OVERSAMPLING INTERPOLATION FILTER:
Stopband Attenuation: –82dB
Passband Ripple: ±0.002dB
q SAMPLING FREQUENCY: 10kHz to 200kHz
q ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO DATA
q DATA FORMATS: Standard, I2S, and Left-Justified
q SYSTEM CLOCK: 128/192/256/384/512/768fS
q USER-PROGRAMMABLE FUNCTIONS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Soft Mute
Zero Detect Mute
Zero Flags May Be Used As General
Purpose Logic Outputs
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
q DUAL SUPPLY OPERATION:
+5V Analog, +3.3V Digital
q 5V TOLERANT DIGITAL LOGIC INPUTS
q PACKAGES(1): LQFP-48 (PCM1604) and
MQFP-48 (PCM1605)
APPLICATIONS
q INTEGRATED A/V RECEIVERS
q DVD MOVIE AND AUDIO PLAYERS
q HDTV RECEIVERS
q CAR AUDIO SYSTEMS
q DVD ADD-ON CARDS FOR HIGH-END PCs
q DIGITAL AUDIO WORKSTATIONS
q OTHER MULTI-CHANNEL AUDIO SYSTEMS
DESCRIPTION
The PCM1604(1) and PCM1605(1) are CMOS mono-
lithic integrated circuits which feature six 24-bit audio
digital-to-analog converters, and support circuitry in a
small QFP-48 package. The digital-to-analog convert-
ers utilize Burr-Brown’s enhanced multi-level, delta-
sigma architecture, which employs 4th-order noise
shaping and 8-level amplitude quantization to achieve
excellent signal-to-noise performance, and a high tol-
erance to clock jitter.
The PCM1604 and PCM1605 accept industry-stan-
dard audio data formats with 16- to 24-bit audio data.
Sampling rates up to 200kHz are supported. A full set
of user-programmable functions are accessible through
a 4-wire serial control port which supports register
write and readback functions.
NOTE: (1) The PCM1604 and PCM1605 utilize the same die and are
electrically identical. All references to the PCM1604 apply equally to
the PCM1605.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 2000 Burr-Brown Corporation
PDS-1564A
Printed in U.S.A. April, 2000

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PCM1604Y pdf
PIN ASSIGNMENTS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
NAME
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
AGND
VCC
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VCOM2
VCOM1
AGND6
VCC6
AGND5
VCC5
AGND4
VCC4
AGND3
VCC3
AGND2
VCC2
AGND1
VCC1
AGND0
VCC0
NC
NC
MDO
MDI
MC
ML
RST
SCKI
SCKO
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
O
40 BCK I
41 LRCK I
42
TEST
43
VDD
44
DGND
45 DATA1 I
46 DATA2 I
47 DATA3 I
48
ZEROA
O
DESCRIPTION
Zero Data Flag for VOUT1. Can also be used as GPO pin.
Zero Data Flag for VOUT2. Can also be used as GPO pin.
Zero Data Flag for VOUT3. Can also be used as GPO pin.
Zero Data Flag for VOUT4. Can also be used as GPO pin.
Zero Data Flag for VOUT5. Can also be used as GPO pin.
Zero Data Flag for VOUT6. Can also be used as GPO pin.
Analog Ground
Analog Power Supply, +5V
Voltage Output for Audio Signal Corresponding to Rch on DATA3.
Voltage Output for Audio Signal Corresponding to Lch on DATA3.
Voltage Output for Audio Signal Corresponding to Rch on DATA2.
Voltage Output for Audio Signal Corresponding to Lch on DATA2.
Voltage Output for Audio Signal Corresponding to Rch on DATA1.
Voltage Output for Audio Signal Corresponding to Lch on DATA1.
Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND.
Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND.
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
No Connection. Must be open.
No Connection. Must be open.
Serial Data Output for Function Register Control Port(3)
Serial Data Input for Function Register Control Port(1)
Shift Clock for Function Register Control Port(1)
Latch Enable for Function Register Control Port(1)
System Reset, Active LOW(1)
System Clock In. Input frequency is 128, 192, 256, 384, 512 or 768fS.(2)
Buffered Clock Output. Output frequency is 128, 192, 256, 384, 512, or 768fS or one-half of 128, 192, 256, 384, 512,
or 768fS.
Shift Clock Input for Serial Audio Data(2)
Left and Right Clock Input. This clock is equal to the sampling rate, fS.(2)
Test Pin. This pin should be connected to DGND.(1)
Digital Power Supply, +3.3V
Digital Ground for +3.3V
Serial Audio Data Input for VOUT1 and VOUT2(2)
Serial Audio Data Input for VOUT3 and VOUT4(2)
Serial Audio Data Input for VOUT5 and VOUT6(2)
Zero Data Flag. Logical “AND” of ZERO1 through ZERO6.
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.
®
5 PCM1604, PCM1605

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PCM1604Y arduino
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1604 and PCM1605 require a system clock for
operating the digital interpolation filters and multi-level
delta-sigma modulators. The system clock is applied at the
SCKI input (pin 38). Table I shows examples of system
clock frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1604 system clock source.
To obtain optimal dynamic performance when operating
with a 192kHz sampling frequency, it is recommended that
only two channels be enabled for operation (VOUT1 and
VOUT2). The remaining four channels should be disabled by
setting bits DAC3 through DAC6 of control register 8 to
logic 1 state.
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the SCKO output (pin 39). SCKO can operate at either full
(fSCKI) or half (fSCKI/2) rate. The SCKO output frequency
may be programmed using the CLKD bit of Control Regis-
ter 9. The SCKO output pin can also be enabled or disabled
using the CLKE bit of Control Register 9. The default is
SCKO enabled.
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1604 includes a power-on reset function. Figure 2
shows the operation of this function.
The system clock input at SCKI should be active for at least
one clock period prior to VDD = 2.0V. With the system clock
active and VDD > 2.0V, the power-on reset function will be
enabled. The initialization sequence requires 1024 system
clocks from the time VDD > 2.0V. After the initialization
period, the PCM1604 will be set to its reset default state, as
described in the Mode Control Register section of this data
sheet.
The PCM1604 also includes an external reset capability
using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1604 to
initialize to its reset default state. For normal operation, RST
should be set to a logic ‘1’.
Figure 3 shows the external reset operation and timing. The
RST pin is set to logic ‘0’ for a minimum of 20ns. The RST
pin is then set to a logic ‘1’ state, which starts the initializa-
tion sequence, which lasts for 1024 system clock periods.
After the initialization sequence is completed, the PCM1604
will be set to its reset default state, as described in the Mode
Control Registers section of this data sheet.
The external reset is especially useful in applications where
there is a delay between PCM1604 power up and system
clock activation. In this case, the RST pin should be held at
a logic ‘0’ level until the system clock has been
activated.
SAMPLING FREQUENCY
(fS)
16kHz
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192
128fS
12.2880
22.5792
24.5760
192fS
18.4320
33.8688
36.8640
SYSTEM CLOCK FREQUENCY (fSCKI)
(MHz)
256fS
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
See Note 2
See Note 2
384fS
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
See Note 2
See Note 2
512fS
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
See Note 2
See Note 2
768fS
12.2880
24.5760
33.8688
36.8640
See Note 1
See Note 1
See Note 2
See Note 2
NOTE: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock rate is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
“H”
SCKI
“L”
tSCKIH
tSCKIH
System Clock Pulse Width High tSCKIH
System Clock Pulse Width Low tSCKIL
fSCKI
: 7ns min
: 7ns min
FIGURE 1. System Clock Input Timing.
2.0V
0.8V
11 PCM1604, PCM1605
®

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