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PDF ZN427J8 Data sheet ( Hoja de datos )

Número de pieza ZN427J8
Descripción MICROPROCESSOR COMPATIBLE 8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER
Fabricantes Zarlink Semiconductor Inc 
Logotipo Zarlink Semiconductor Inc Logotipo



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ZN427E8 / ZN427J8
MICROPROCESSOR COMPATIBLE
8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER
The ZN427 is an 8-bit successive approximation converter
with three-state outputs to permit easy interfacing to a
common data bus. The IC contains a voltage switching DAC,
a fast comparator, successive approximation logic and a
2.56V precision bandgap reference, the use of which is pin
optional to retain flexibility. An external fixed or varying
reference may therefore be substituted, thus allowing
ratiometic operation
Only passive external components are required for
operation of the converter.
FEATURES
s Easy Interfacing to Microprocessor, or Operates as a
'Stand-Alone' Converter
s Fast: 10 microseconds Conversion time Guaranteed
s No Missing Codes over Operating Temperature Range
s Data Outputs Three-State TTL Compatible, other
Logic Inputs and Output TTL and CMOS Compatible
s Choice of On-Chip or External Reference Voltage
s Ratiometric Operation
s Unipolar or Bipolar Input Ranges
s Complementary to ZN428 DAC
s Commercial or Military Temperature Range
BUSY (END OF CONVERSION) 1
RD (OUTPUT ENABLE) 2
CLOCK 3
WR (START CONVERSION) 4
REXT 5
VIN
VREF IN
6
7
VREF OUT 8
GROUND 9
18 BIT 8 (LSB)
17 BIT 7
16 BIT 6
15 BIT 5
14 BIT 4
13 BIT 3
12 BIT 2
11 BIT 1 (MSB)
10 +VCC (+5V)
ZN427J8 (DC18)
ZN427E8 (DP18)
Fig.1 Pin connection - top view
ORDERING INFORMATION
Device type Operating temperature
ZN427E8
ZN427J8
0°C to +70°C
-55°C to +125°C
Package
DP18
DC18
D TO A OUTPUT
COMPARATOR
-
VIN 6
REXT 5
CLOCK
INPUT
3
+
R-2R LADDER
ANALOGUE VOLTAGE SWITCHES
SUCCESSIVE
APPROXIMATION REGISTER
VCC
(+5V)
10
3-STATE BUFFERS
11 12 13 14 15 16 17 18
MSB
LSB
Fig.2 System diagram
+2.5V
REFERENCE
8
VREF OUT
9
GROUND
7
VREF IN
4
WR (START CONVERSION)
1
BUSY (END CONVERSION)
2
RD (OUTPUT ENABLE)

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ZN427J8 pdf
ZN427
(c) The write pulse timing criteria make it unsuitable for direct
use as a start conversion pulse.
If any of these conditions apply then the self-synchronising
clock circuit of Fig.5a is recommended.
Fig.5a Self-synchronising clock circuit
Fig.5b Timing diagram for circuit of Fig.5a
5

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ZN427J8 arduino
UNIPOLAR OPERATION
The general connection for unipolar operation is shown in
Fig.14.
The values of R1 and R2 are chosen so that VIN = VREF IN when
the analogue input (AIN) is at full-scale.
The resulting full-scale range is given by:
AINFS =
1
+
R
1
R
, VREF IN = G.VREF IN.
2
ZN427
To match the ladder resistance R1/R2 (RIN) = 4k.
The required nominal values of R1 and R2 are given by
R = 4Gk, R = 4G
12
k
G-1
AIN VREF IN
ZERO
ADJUST
1M
R1
680k
VIN 6
7
ZN427
9
GROUND
R2
Fig.14 Unipolar operation - general connection
Using these relationships a table of nominal values of R1 and
R2 can be constructed for VREF IN = 2.5V.
Input range
G
R
1
R
2
+5V
+10V
2 8k8k
4
16k
5.33k
Gain adjustment
Due to tolerance in R1 and R2, tolerance in VREF and the gain
(full-scale) error of the DAC, some adjustment should be
incorporated into R1 to calibrate the full-scale of the converter.
When used with the internal reference and 2% resistors a
preset capable of adjusting R1 by at least ±5% of its nominal
value is suggested.
Zero adjustment
Due to offsets in the DAC and comparator the zero (0 to 1)
code transition would occur with typically 15mV applied to the
comparator input, which correpsonds to 1.5LSB with a 2.56V
reference.
Zero adjustment must therefore be provided to set the zero
transition to its correct value of +0.5LSB or 5mV with a 2.56V
reference. This is achieved by applying an adjustable positive
offset to the comparator input via P2 and R3. The values
shown are suitable for all input ranges greater than 1.5 times
VREF IN.
Practical circuit values for +5 and +10V input ranges are given
in Fig.15, which incorporates both zero and gain adjustments.
11

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