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PDF PCK2010DL Data sheet ( Hoja de datos )

Número de pieza PCK2010DL
Descripción CK98 100/133MHz Spread Spectrum System Clock Generator
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
PCK2010
CK98 (100/133MHz) Spread Spectrum
System Clock Generator
Preliminary specification
1999 Mar 01
Philips
Semiconductors

1 page




PCK2010DL pdf
Philips Semiconductors
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
168-pin SDR SDRAM DIMM
BACK SIDE
Preliminary specification
PCK2010
FRONT SIDE
AVC
AVC
AVC
PCK2509S or PCK2510S
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00403
FUNCTION TABLE
SEL
133/100
SEL1
SEL0
CPU
CPUDIV2
3V66
PCI 48MHz
REF
IOAPIC
0 0 0 HI-Z HI-Z HI-Z HI-Z HI-Z
HI-Z
HI-Z
0 0 1 N/A N/A N/A N/A N/A
N/A
N/A
0 1 0 100MHz 50MHz 66MHz 33MHz HI-Z 14.318MHz 16.67MHz
0 1 1 100MHz 50MHz 66MHz 33MHz 48MHz 14.318MHz 16.67MHz
1
0
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
1 0 1 N/A N/A N/A N/A N/A
N/A
N/A
1 1 0 133MHz 66MHz 66MHz 33MHz HI-Z 14.318MHz 16.67MHz
1 1 1 133MHz 66MHz 66MHz 33MHz 48MHz 14.318MHz 16.67MHz
NOTES:
1. Required for board level ‘‘bed-of-nails” testing.
2. Used to support Intel confidential application.
3. 48MHz PLL disabled to reduce component jitter. 48MHz outputs to be held Hi-Z instead of driven to LOW state.
4. ‘‘Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316MHz, NOMINAL = 14.31818MHz, MAX = 14.32MHz
NOTES
1
2
3
4, 7, 8
5, 6
2
3
4, 7, 8
CLOCK OUTPUT
USBCLK7
TARGET FREQUENCY (MHz)
48.0
ACTUAL FREQUENCY (MHz)
48.008
PPM
167
1999 Mar 01
5

5 Page





PCK2010DL arduino
Philips Semiconductors
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
Preliminary specification
PCK2010
AC CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
Measurement loads
(lumped)
Measure points
LIMITS
Tamb = 0°C to +70°C
MIN TYP MAX
UNIT NOTES
THPOFFSET
CPUCLK to 3V66 CLK, CPU
leads
CPU@30pF,
3V66@30pF
0.0
1.5 ns
1
THPOFFSET
3V66 CLK to PCICLK, 3V66
leads
3V66@30pF,
PCI@30pF
1.5
3.5 ns
1
THPOFFSET
CPUCLK to IOAPIC, CPU
leads
CPU@20pF,
IOAPIC@20pF
1.5
4.0 ns
1
PCICLK to CPUCLK, CPU
leads
PCI@30pF
CPU@30pF
5.8 ns
CPUDIV2 to CPUCLK,
CPUDIV2 leads
CPUDIV2@20pF
CPU@30pF
CPUDIV2@
1.6 ns
IOAPICCLK to CPUCLK,
IOAPIC leads
IOAPIC@20pF
CPU@30pF
IOAPIC@20pF
3.7 ns
3V66 CLK to CPUCLK, 3V66
leads
3V66@30pF
CPU@30pF
1.7 ns
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133.MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK
= 100MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100MHz.
5. THKH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs as shown in Figure 4.
6. THKL is measured at 0.4V for all outputs as shown in Figure 4.
7. The time is specified from when VDDQ achieves its nominal operating level (typical condition VDDQ = 3.3V) until the frequency output is
stable and operating within specification.
8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1mA) JEDEC specification.
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 3 for measure points).
PCK2010 SPREAD SPECTRUM FUNCTION TABLE
SPREAD# SEL133/100# SEL1 SEL0
Intel CK133
pin 34
0 (active)
pin 28
pin 33 pin 32
Function
0 (100MHz) 0
0
3-State to
High Impedance
0 (active) 0 (100MHz) 0 1 (Reserved)
0 (active) 0 (100MHz) 1
0
100MHz, Down
Spread – 0.5%
0 (active) 0 (100MHz) 1
1
100MHz, Down
Spread – 0.5%
0 (active) 1 (133MHz) 0 0 Test Mode
0 (active) 1 (133MHz) 0 1 (Reserved)
0 (active) 1 (133MHz) 1
0
133Mhz, Down
Spread – 0.5%
0 (active) 1 (133MHz) 1
1
133Mhz, Down
Spread – 0.5%
1 (inactive) 0 (100MHz) 0
0
3-State to
High Impedance
Intel CK133
Philips PCK2010
48MHz PLL
Inactive
(Reserved)
Inactive
Active
Active
(Reserved)
Inactive
Active
Inactive
Function
3-State to
High Impedance
100MHz, Center
Spread ±0.5%
100MHz, Down
Spread – 0.5%
100MHz, Down
Spread – 0.5%
Test Mode
133MHz, Center
Spread ±0.5%
133MHz, Down
Spread – 0.5%
133MHz, Down
Spread – 0.5%
3-State to
High Impedance
Philips
PCK2010
48MHz PLL
Inactive
Active
Inactive
Active
Active
Active
Inactive
Active
Inactive
1999 Mar 01
11

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