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PDF X1286 Datasheet ( Hoja de datos )

Número de pieza X1286
Descripción Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo
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X1286 datasheet

1 Page

X1286 pdf
X1286
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
Address Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a
stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the
Slave Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10)VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC
(11)IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15)Typical values are for TA = 25°C
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1)
CIN(1)
Output Capacitance (SDA, PHZ/IRQ)
Input Capacitance (SCL)
10 pF
10 pF
VOUT = 0V
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard Output Load
Figure 1. Standard Output Load for testing the device with VCC = 5.0V
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
5.0V
SDA
1533
For VOL= 0.4V
and IOL = 3 mA
100pF
PHZ/IRQ
1316
806
100pF
REV 1.1 7/8/04
www.intersil.com
5 of 26

5 Page

X1286 arduino
X1286
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
*n = 0 for Alarm 0: N = 1 for Alarm 1
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
Table 1. Clock/Control Memory Map
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
Type
Status
RTC
(SRAM)
Control
(EEPROM)
Reg
Name
SR
SSEC
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
BL
7
BAT
SS23
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
6
AL1
SS22
0
Y22
0
0
0
M22
S22
0
0
AL1E
BP1
5
AL0
SS21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
BP0
Bit
4
0
SS20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
FO1
WD1
3
0
SS13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
FO0
WD0
0
2 1 (optional) Range
RWEL
WEL
RTCF
SS12
SS11
SS10 0-99
DY2 DY1 DY0 0-6
Y12 Y11 Y10 0-99
G12 G11 G10 1-12
D12 D11 D10 1-31
H12 H11 H10 0-23
M12 M11 M10 0-59
S12 S11 S10 0-59
DTR2
DTR1
DTR0
ATR2
ATR1
ATR0
Read Only Read Only Read Only
Read Only Read Only Read Only
01h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
00h
00h
REV 1.1 7/8/04
www.intersil.com
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