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PDF X1243V8 Datasheet ( Hoja de datos )

Número de pieza X1243V8
Descripción Real Time Clock/Calendar/Alarm with EEPROM
Fabricantes Xicor 
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X1243V8 datasheet

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X1243V8 pdf
X1243
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The Clock
Default values define 0=Sunday.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the time.
As such, SC (Seconds) and MN (Minutes) range from
00 to 59, HR (Hour) is 1 to 12 with an AM or PM indica-
tor (H21 bit) or 0 to 23 (with T24=1), DT (Date) is 1 to
31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
24 Hour Time
If the T24 bit of the HR register is 1, the RTC will use a
24-hour format. If the T24 bit is 0, the RTC will use 12-
hour format and bit H21 will function as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
Standard Time with H21=0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible by
400. This means that the year 2000 is a leap year, the
year 2100 is not. The X1243 does not correct for the
leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, read an optional Low Voltage Sense bit, and
read the two alarm bits. This register is logically seper-
ated from both the array and the Clock/Control Regis-
ters (CCR).
Table 2. Status Register (SR)
Addr 7 6 5 4
003Fh BAT AL1 AL0 0
Default 0 0 0 0
32 1 0
0 RWEL WEL RTCF
00 0 0
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read only bit and is set/
reset by hardware.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective bit
is set to ‘1’. The falling edge of the last data bit in a SR
Read operation resets the flags. Note: Only the AL bits
that are set when an SR read starts will be reset. An
alarm bit that is set by an alarm occuring during an SR
read operation will remain set after the read operation
is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both the
RWEL and WEL bits to be set in a specific sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to 0 (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part pow-
ers up again. Writes to WEL bit do not cause a non-vol-
atile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware when the device
powers up after having lost all power to the device. The
bit is set regardless of whether VCC or VBACK is applied
first. The loss of one or the other supplies does not
result in setting the RTCF bit. The first valid write to the
RTC (writing one byte is sufficient) resets the RTCF bit
to ‘0’.
Unused Bits:
These devices do not use bits 3 or 4, but must have a
zero in these bit positions. The Data Byte output during
a SR read will contain zeros in these bit locations.
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X1243V8 arduino
X1243
the address counter would point to location 7 on the
page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over written by the new data, one byte
at a time.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the device to begin
the non-volatile write cycle. As with the byte write
operation, all inputs are disabled until completion of
the internal write cycle. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The disabling of the inputs during non-volatile write
cycles can be used to take advantage of the typical
5mS write cycle time. Once the stop condition is
issued to indicate the end of the master’s byte load
operation, the device initiates the internal non-volatile
write cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start con-
dition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the non-
volatile write cycle then no ACK will be returned. If the
device has completed the write operation, an ACK will
be returned and the host can then proceed with the read
or write operation. Refer to the flow chart in Table 9.
READ OPERATIONS
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read can be initiated immediately after the
power on reset to download the contents of memory
starting at the first location.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave
Address Byte
(Read or Write)
ACK
returned?
YES
nonvolatile write
Cycle complete.
Continue command
sequence?
YES
Continue normal
Read or Write
command
sequence
Issue STOP
NO
NO
Issue STOP
PROCEED
Figure 9. Acknowledge Polling Sequence
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 10
for the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
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