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PDF X1243S8 Datasheet ( Hoja de datos )

Número de pieza X1243S8
Descripción Real Time Clock/Calendar/Alarm with EEPROM
Fabricantes Xicor 
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X1243S8 datasheet

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X1243S8 pdf
X1243
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The Clock
Default values define 0=Sunday.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the time.
As such, SC (Seconds) and MN (Minutes) range from
00 to 59, HR (Hour) is 1 to 12 with an AM or PM indica-
tor (H21 bit) or 0 to 23 (with T24=1), DT (Date) is 1 to
31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
24 Hour Time
If the T24 bit of the HR register is 1, the RTC will use a
24-hour format. If the T24 bit is 0, the RTC will use 12-
hour format and bit H21 will function as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
Standard Time with H21=0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible by
400. This means that the year 2000 is a leap year, the
year 2100 is not. The X1243 does not correct for the
leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, read an optional Low Voltage Sense bit, and
read the two alarm bits. This register is logically seper-
ated from both the array and the Clock/Control Regis-
ters (CCR).
Table 2. Status Register (SR)
Addr 7 6 5 4
003Fh BAT AL1 AL0 0
Default 0 0 0 0
32 1 0
0 RWEL WEL RTCF
00 0 0
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read only bit and is set/
reset by hardware.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective bit
is set to ‘1’. The falling edge of the last data bit in a SR
Read operation resets the flags. Note: Only the AL bits
that are set when an SR read starts will be reset. An
alarm bit that is set by an alarm occuring during an SR
read operation will remain set after the read operation
is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both the
RWEL and WEL bits to be set in a specific sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to 0 (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part pow-
ers up again. Writes to WEL bit do not cause a non-vol-
atile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware when the device
powers up after having lost all power to the device. The
bit is set regardless of whether VCC or VBACK is applied
first. The loss of one or the other supplies does not
result in setting the RTCF bit. The first valid write to the
RTC (writing one byte is sufficient) resets the RTCF bit
to ‘0’.
Unused Bits:
These devices do not use bits 3 or 4, but must have a
zero in these bit positions. The Data Byte output during
a SR read will contain zeros in these bit locations.
5

5 Page

X1243S8 arduino
X1243
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a Slave
r Address
t
1 1111
A
C
K
Data
S
t
o
p
Figure 10. Current Address Read Sequence
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 11 for the address,
acknowledge, and data transfer sequence.
In a similar operation, called “Set Current Address,”
the device sets the address if a stop is issued instead of
the second start shown in Figure 11. The X1243 then
goes into standby mode after the stop and all bus activity
will be ignored until a start is detected. This operation
loads the new address into the address counter. The next
Current Address Read operation will read from the
newly loaded address. This operation could be useful
if the master knows the next address it needs to read,
but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory
contents to be serially read during one operation. At
the end of the address space the counter “rolls over” to
the start of the address space and the device continues
to output data for each acknowledge received. Refer
to Figure 12 for the acknowledge and data transfer
sequence.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
Word
Address 1
Word
Address 0
S
t
a Slave
r Address
t
1 1 1 1 0 0 0 0 00
A
C
K
A
C
K
1
A
C
K
1111
A
C
K
Data
S
t
o
p
Figure 11. Random Address Read Sequence
11

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