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PDF X1205 Datasheet ( Hoja de datos )

Número de pieza X1205
Descripción Real Time Clock/Calendar
Fabricantes Xicor 
Logotipo Xicor Logotipo

Total 22 Páginas
		
X1205 Hoja de datos, Descripción, Manual
Preliminary Information
New Features
Repetitive Alarms &
Temperature Compensation
X1205
Real Time Clock/Calendar
2-WireRTC
FEATURES
• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 2-Wire™ Interface interoperable with I2C*
—400kHz data transfer rate
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8-Lead SOIC and 8-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with clock/
calendar, two polled alarms, oscillator compensation,
and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, and Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.
BLOCK DIAGRAM
OSC
Compensation
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
IRQ
Control
Decode
Logic
8
*I2C is a Trademark of Philips.
REV 1.0.9 8/29/02
Control
Registers
(EEPROM)
Status
Registers
(SRAM)
Interrupt Enable
Alarm
www.xicor.com
Alarm
Compare
Alarm Regs
(EEPROM)
Characteristics subject to change without notice. 1 of 22

1 page

X1205 pdf
X1205 – Preliminary Information
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1205 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
Addr 7
003Fh BAT
Default 0
65
AL1 AL0
00
4
0
0
3
0
0
2
RWEL
0
10
WEL RTCF
01
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read-only bit and is set/
reset by hardware (X1205 internally). Once the device
begins operating from VCC, the device sets this bit to
“0”.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1205 inter-
nally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether VCC or VBACK is applied first. The loss of only
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice. 5 of 22

5 Page

X1205 arduino
X1205 – Preliminary Information
Random Read
Random read operations allow the master to access
any location in the X1205. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt of
each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 10. The X1205 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received. The mas-
ter terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
Refer to Figure 11 for the acknowledge and data trans-
fer sequence.
Figure 10. Random Address Read Sequence
Signals from
the Master
S
t
a
Slave
r Address
t
Word
Address 1
Word
Address 0
S
t
a Slave
r Address
t
SDA Bus
Signals from
the Slave
11 011 11 0 00 000 00
A
C
K
A
C
K
11 011 1 11
AA
CC
KK
Data
S
t
o
p
Figure 11. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
A AA
Address C C C
K KK
1
A
C Data
K (1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
S
t
o
p
REV 1.0.9 8/29/02
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Characteristics subject to change without notice. 11 of 22

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