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PDF WT62P1 Data sheet ( Hoja de datos )
| Número de pieza | WT62P1 | |
| Descripción | microcontroller for digital controlled monitor with Universal Serial Bus (USB) interface | |
| Fabricantes | ETC | |
| Logotipo |  |
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WT62P1
Data Sheet Rev. 1.01
GENERAL DESCRIPTION
The WT62P1 is a microcontroller for digital controlled monitor with Universal Serial Bus (USB) interface.
It contains an 8-bit CPU, 32K bytes flash memory, 512 bytes RAM, 14 PWMs, parallel I/Os, SYNC signal
processor, timer, DDC1/2B interface, master/slave I2C interface, low speed USB device module, 6-bit
A/D converter and watch-dog timer.
FEATURES
• 8-bit 6502 compatible CPU with 6MHz operating frequency
• 32768 bytes flash memory, 512 bytes SRAM
• 12MHz crystal oscillator
• 14 channels 8-bit PWM outputs
• Sync signal processor with H+V separation, H/V frequency counter, H/V polarity detection/control and
clamp pulse output
• Six free-running sync signal outputs (Horizontal frequency up to 106KHz)
• Self-test pattern
• DDC1/2B supported
• Fast mode master/slave I2C interface (up to 400KHz)
• Embedded USB function with endpoint 0 and endpoint 1
• Built-in 3.3V regulator for USB tranceiver
• Watch-dog timer
• Maximum 28 programmable I/O pins
• One 8-bit programmable timer
• 6-bit A/D converter with 4 selectable inputs
• One external interrupt request input
• Low VDD reset
ORDERING INFORMATION
Package Type
42-pin PDIP
42-pin Shrink PDIP
40-pin PDIP
28-pin skinny PDIP
44-pin SOP
Part Number
WT62P1-N42
WT62P1-K42
WT62P1-N40
WT62P1-N28
WT62P1-S44
Weltrend Semiconductor, Inc.
Page 2
1 page  
WT62P1
Data Sheet Rev. 1.01
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Fig. 1 Reset Signals
External Reset
A low level on the RESET/3.3V pin will generate reset.
Illegal address Reset
When the address bus of CPU goes to illegal address, a reset pulse will be generated.
The illegal address is defined as $0040h~$007Fh, $0300h~$0FFEh and $1000h~$7FFFh.
Low VDD Voltage Reset
When VDD is below 3.9V, an internal reset signal is generated. The reset signal will last 2.048 ms after
the voltage is higher than 3.9V.
Watchdog Timer Reset
If a time-out happens when watchdog timer is enabled, a reset pulse is generated. Please refer
watchdog timer section for more information.
Weltrend Semiconductor, Inc.
Page 6
5 Page 
WT62P1
Data Sheet Rev. 1.01
Vertical frequency counter
A 13-bit counter is used to measure the time interval between two vertical sync pulses. It will be updated
every vertical frame. The clock of this counter is 125kHz. So the frequency of Vsync is [125000 / (counter
value + 1)] Hz. When V frequency is lower than 15.25Hz, this counter stops counting and set VOVF bit to
“ 1” .
Vertical Frequency Register
Name Addr R/W Initial Bit 7
VFREQ_L 000Ah R xxh VF7
VFREQ_H 000Bh R xxh VLVL
Bit 6
VF6
VINPOL
Bit 5
VF5
VOVF
Bit4
VF4
VF12
Bit 3
VF3
VF11
Bit 2
VF2
VF10
Bit 1
VF1
VF9
Bit 0
VF0
VF8
Bit Name
Description
VLVL “ 1” : Indicates Vsync pin is high level.
“ 0” : Indicates Vsync pin is low level.
VNPOL “ 1” : Indicates Vsync input is positive polarity.
“ 0” : Indicates Vsync input is negative polarity.
VOVF Indicates V counter is overflowed when this is set. Vsync frequency is lower than 15.25Hz
VF12 ~ VF0 Indicates the Vertical Total Time. Vertical frequency is [125000 / (counter value +1) ] Hz
Example of Vsync Frequency Calculation
VF12..0 Max. Freq Min. Freq VF12..0
$05BDh 85.15Hz 85.034Hz $0783h
$05BEh 85.092Hz 84.976Hz $0784h
$05BFh 85.034Hz 84.918Hz $0785h
$0681h 75.12Hz
75.03Hz
$0823h
$0682h 75.075Hz 74.985Hz $0824h
$0683h 75.03Hz
74.94Hz
$0825h
$06C7h 72.088Hz 72.005Hz $1FFEh
$06C8h 72.046Hz 71.963Hz $1FFEh
$06C9h 72.005Hz 71.921Hz $1FFFh
Max. Freq
65.036Hz
65.003Hz
64.969Hz
60.038Hz
60.01Hz
59.981Hz
15.266Hz
15.264Hz
15.262Hz
Min. Freq
64.969Hz
64.935Hz
64.901Hz
59.981Hz
59.952Hz
59.923Hz
15.262Hz
15.260Hz
15.258Hz
Hsync period counter
This is an 8-bit counter that uses 6MHz clock to measure time interval between two H pulses. If the H
frequency is lower than 23437.5Hz, this counter will overflow and register H_PERD value is zero.
Horizontal Period Register
Name Addr R/W Initial Bit 7
H_PERD 000Ch R xxh HPRD7
Bit 6
HPRD6
Bit 5
HPRD5
Bit4
HPRD4
Bit 3
HPRD3
Bit 2
HPRD2
Bit 1
HPRD1
Bit 0
HPRD0
Bit Name Description
HPRD7 .. 0 H freq = 6MHz / (counter value+1)
Example of Hsync Frequency Calculation
HPRD7..0 Max. Freq Min. Freq HPRD7..0
$49h 83.333KHz 81.081KHz $7Ch
$4Ah 82.192KHz 80KHz
$7Dh
$4Bh 81.081KHz 78.947KHz $7Eh
$5Dh 65.217KHz 63.83KHz
$BFh
$5Eh 64.516KHz 63.158KHz $C0h
$5Fh
63.83KHz 62.5KHz
$C1h
Max. Freq
48.78KHz
48.387KHz
48KHz
31.579KHz
31.414KHz
31.25KHz
Min. Freq
48KHz
47.619KHz
47.244KHz
31.25KHz
31.088KHz
30.928KHz
Weltrend Semiconductor, Inc.
Page 12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WT62P1.PDF ] | |
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