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PDF WM8510 Data sheet ( Hoja de datos )

Número de pieza WM8510
Descripción MONO CODEC WITH SPEAKER DRIVER
Fabricantes Wolfson Microelectronics plc 
Logotipo Wolfson Microelectronics plc Logotipo



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WM8510
Mono CODEC with Speaker Driver
DESCRIPTION
FEATURES
The WM8510 is a low power, high quality mono codec designed
for Voice over Internet Protocol (VoIP) and Digital Telephones.
The device integrates support for one pseudo-differential and
one single ended input (Handset Mic and Speaker Mic) and
includes drivers for speakers or headset, and mono line output,
making it ideal for Telephone designs. External component
requirements are reduced as no separate microphone or
earpiece amplifiers are required.
Advanced Sigma Delta Converters are used along with digital
decimation and interpolation filters to give high quality audio at
sample rates from 8 to 48kHz.
Additional digital filtering options are available in the ADC path,
to cater for application filtering such as ‘wind noise reduction’,
plus an advanced mixed signal ALC function with noise gate is
provided.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can also
be output if required elsewhere in the system.
The WM8510 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. The speaker and mono outputs use a
separate supply of up to 5V which enables increased output
power if required. Different sections of the chip can also be
powered down under software control by way of the selectable
two or three wire control interface.
WM8510 is supplied in a convenient 28-lead SSOP package,
offering high levels of functionality in an easy to use package.
BLOCK DIAGRAM
Mono Codec:
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1,
48kHz
DAC SNR 93dB, THD -84dB (‘A’-weighted @ 8 – 48kHz)
ADC SNR 90dB, THD -80dB (‘A’-weighted @ 8 – 48kHz)
On-chip Headphone/Speaker Driver with ‘cap-less’ connect
- 40mW output power into 16/ 3.3V SPKVDD
- BTL speaker drive 0.8W into 8/ 5V SPKVDD
Earpiece Line output
Multiple analog inputs, plus analog bypass path (0 or -10dB)
Mic Preamps:
Two Microphone Interfaces
- One pseudo-differential input with common mode
rejection
- One single ended input
- Programmable preamp gain
- Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for microphone
Other Features
Digital Playback Limiter
Programmable ADC High Pass Filter (wind noise reduction)
Programmable ADC Notch Filter
On-chip PLL
Low power, low voltage
- 2.5V to 3.6V (digital supplies: 1.71V to 3.6V)
- power consumption <10mW all-on 48kHz mode
28 lead SSOP package
APPLICATIONS
VoIP Telephones
Digital Telephones
Conference Speaker-phone
Mobile Telephone Hands-free Kits
General Purpose low power audio CODEC
MIC2
NOISY
GNDMICN
Mic
MICP
Rbias
MICBIAS
20k
20k
Gains
: -12dB to
+35.25dB
IP PGA
IP BOOST/MIX
25k 25k
4k 5k 250k 250k
I2 S or PCM
INTERFACE
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WM8510
ADC
ADC
DIGITAL
FILTERS
DAC
DIGITAL
FILTERS
Volume
Limiter /
ALC
Wind Noise
Filters
Volume
Digital
Limiter
DAC
SIDETONE
PLL
CONTROL
INTERFACE
-10dB or +0dB
MONO OUT
-10dB or +0dB
-1
SPKR PGA
SPKOUTP
L - (-R)
= L+R
SPKOUTN
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Production Data, September 2008, Rev 4.5
Copyright ©2008 Wolfson Microelectronics plc

1 page




WM8510 pdf
Production Data
WM8510
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
DBVDD, DCVDD, AVDD supply voltages
SPKVDD supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, TA
Storage temperature after soldering
Notes
MIN
-0.3V
-0.3V
DGND -0.3V
AGND -0.3V
-40°C
-65°C
1. Analogue and digital grounds must always be within 0.3V of each other.
2. All digital and analogue supplies are completely independent from each other.
3. When using the PLL, DCVDD should be 1.9V
MAX
+3.63V
+7V
DVDD +0.3V
AVDD +0.3V
+85°C
+150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Speaker supply
Ground
Notes
1. DCVDD DBVDD at all times.
DCVDD
DBVDD
AVDD
SPKVDD
DGND,AGND, SPKGND
TEST
CONDITIONS
MIN
1.71
1.71
2.5
2.5
TYP
MAX
UNIT
3.6 V
3.6 V
3.6 V
5.5 V
0V
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PD, Rev 4.5, September 2008
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WM8510 arduino
Production Data
CONTROL INTERFACE TIMING – 3-WIRE MODE
WM8510
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz,
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
SYMBOL
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tps
MIN TYP MAX UNIT
80 ns
200 ns
80 ns
80 ns
40 ns
40 ns
40 ns
40 ns
40 ns
0 5 ns
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PD, Rev 4.5, September 2008
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